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Many of today's Electro-Optical/Infrared (EO/IR) systems require high-complexity, real-time video processing within a constrained power budget. The latest low-power, low-cost FPGA families - with their inherently parallel Digital Signal Processing (DSP) blocks, an abundance of embedded memory blocks, large number of registers, and high-speed memory interfaces - are ideal for developing the next generation of night vision, thermal imaging, head-mounted and avionics displays, and other such EO/IR systems. However, video processing on FPGAs also has challenges, such as implementing efficient external-frame buffer interfaces, interfacing different video function blocks, integrating signal processing to the on-chip processor, as well as the lengthy debug and prototyping cycles.
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