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FPGAs are increasingly being used in the high performance and scientific computing community to implement floating-point based hardware accelerators. The authors present FPGA floating-point multiplication. Such circuits can be extremely useful in the FPGA implementation of complex systems that benefit from the re-programability and parallelism of the FPGA device but also require a general purpose multiplier unit. While previous work has considered circuits for low precision floating-point formats, they consider the implementation of 32-bit Single precision circuits that also provide rounding and exception handling. They introduce an algorithm for multiplication and analyze its performance on Virtex 4 having device (XC4VLX15-SF363) hardware module at speed grade -12.
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