Virtualizing Hardware With Multi-Context Recon Gurable Arrays
In contrast to processors, current reconfigurable devices totally lack programming models that would allow for device independent compilation and forward compatibility. The key to overcome this limitation is hardware virtualization. In this paper, the authors resort to a macro-pipelined execution model to achieve hardware virtualization for data streaming applications. As a hardware implementation they present a hybrid multi-context architecture that attaches a coarse-grained reconfigurable array to a host CPU. A co-simulation framework enables cycle-accurate simulation of the complete architecture. As a case study they map an FIR filter to the virtualized hardware model and evaluate different designs. They discuss the impact of the number of contexts and the feature of context state on the speedup and the CPU load.