VLSI Architecture for Low Power Variable Length Encoding and Decoding for Image Processing Applications
The image data compression has been an active research area for image processing over the last decade and has been used in a variety of applications. This paper investigates the implementation of Low Power VLSI architecture for image compression, which uses Variable Length Coding method to compress JPEG signals. The architecture is proposed for the quantized DCT output. The proposed architecture consists of three optimized blocks, viz, Zigzag scanning, Run-length coding and Huffman coding. In the proposed architecture, Zigzag scanner uses two RAM memories in parallel to make the scanning faster.