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Most of advanced wireless standards, such as WiMAX and LTE, have adopted different Convolutional Turbo Code (CTC) schemes with various block sizes and throughput rates. Thus, a reconfigurable and scalable hardware accelerator for multi standard CTC decoding is necessary. In this paper, the authors propose scalable Maximum A Posteriori algorithm (MAP) processor designs which can support both Single-Binary (SB) and Double-Binary (DB) CTC decoding, and handle arbitrary block sizes for high throughput CTC decoding. They first propose three combinations of Parallel-Window (PW) and Hybrid-Window (HW) MAP decoding. Moreover, the computational modules and storages of the dual-mode Single/Double Binary (SB/DB) MAP decoding are designed to achieve a high area utilization.
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