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Differential Analog Viterbi decoding presents a powerful Forward-Error-Correction (FEC) channel coding for digital communications. Viterbi decoder is widely used in space, satellite, CDMA, Digital, PCS and DVB systems and hence there is a need for efficient, low-power implementation of the Viterbi decoding algorithm. In this paper, modified differential decoder architecture is proposed and implemented using 130nm CMOS technology. The output samples from the sample and hold circuit are converted to current output and is processed. The advantages of working in the current mode are the reduction in number of transistors. The add-compare-select logic is optimized by replacing the adder logic with an optimized adder that consumes 24 transistors. The encoded data is QPSK modulated and the decoder logic operates on I and Q channels.
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