VLSI Design of a 16-Bit Pipelined RISC Processor

In this paper, the authors have described the design of a 16-bit pipelined RISC processor for applications in real-time embedded systems. The processor executes most of the instructions in single machine cycle making it ideal for use in high speed systems. The processor has been designed to be implemented on an FPGA using VHDL such that one can reconfigure it according to specific requirements of the target applications. The processor is powerful enough to be used as a stand-alone processing element and is generic enough to be used in multi-processor System on Chip.

Provided by: International Journal of Electronics and Computer Science Engineering Topic: Data Centers Date Added: Jul 2012 Format: PDF

Download Now

Find By Topic