Vlsi Design of Cache Compression in Microprocessor Using Pattern Matching Technique

Microprocessors speeds have been increasing faster than speed of off-chip memory. When multi processors are used in the system design, more processors require more accesses to memory. Thus it raises a 'wall' between processor and memory. Accessing off-chip memory takes an order of magnitude more time than accessing an on-chip cache, two orders of magnitude more time than executing an instruction. Cache compression presents the challenge that the processor speed has to be improved but it should not substantially increase the total chip's power consumption. This Cellular Automata (CA) based pattern matching architecture has number of novel features tailored for the application.

Provided by: IOSR Journal of Engineering Topic: Data Centers Date Added: Aug 2012 Format: PDF

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