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The authors describe the design, implementation, and evaluation of emulated hardware transactional memory, specifically the Intel Haswell Restricted Transactional Memory (RTM) architectural extensions for x86/64, within a virtual machine monitor (VMM). Their system allows users to investigate RTM on hardware that does not provide it, debug their RTM-based transactional software, and stress test it on diverse emulated hardware configurations. They are able to accomplish this approximately 60 times faster than under emulation. A noteworthy aspect of their system is a novel page-flipping technique that allows them to completely avoid instruction emulation, and to limit instruction decoding to only that necessary to determine instruction length.
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