WCET-Aware Optimization of Shared Cache Partition and Bus Arbitration for Hard Real-Time Multicore Systems
In recent years, multicore processors have been receiving a significant amount of attention from avionic and automotive industries as the demand for high-end real-time applications drastically increases. However, the unpredictable worst-case timing behavior that mainly arises from shared resource contention in current multicore architectures has been the biggest stumbling block for a widespread use of multicores in hard real-time systems. Great deals of research efforts have been devoted to address the issue. Among others, the development of a new multicore architecture has emerged as an attractive solution because it is possible to eliminate the sources of unpredictable interferences in the first place, or at least to turn them into predictable ones.