Hardware

Wirelength Modeling for Homogeneous and Heterogeneous FPGA Architectural Development

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Executive Summary

This paper describes an analytical model that relates the architectural parameters of an FPGA to the average pre-routing wire-length of an FPGA implementation. Both homogeneous and heterogeneous FPGAs are considered. For homogeneous FPGAs, the model relates the lookup-table size, the cluster size, and the number of inputs per cluster to the expected wire-length. For heterogeneous FPGAs, the number and positioning of the embedded blocks, as well as the number of pins on each embedded block is considered. Two applications of the model to FPGA architectural design are also presented.

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