Intel shows off new 22-nanometer wafer
September 22, 2009, 12:29pm PDT | Length: 00:01:17
At the Intel Developer Forum in San Francisco, Intel CEO Paul Otellini shows off a silicon wafer housing chips made with 22-nanometer process technology. Chips made on that process will be ready for market in 2011.
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Transcript
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>> Narrator: We've been working on a new technology, the next generation after 32 which is 22 nanometers. And I can't show you a picture of this transistor here because my guys just won't let me. However, I can show you for the first time ever the world's first working 22 nanometer silicon technology.
Audience clapping
>> Narrator: And it's just not able to show you; it also works. It's the smallest S-Ram cell ever invented. These transistors use a third generation of the high-K Metal gate technology. Each S-Ram chip has 2.9 billion transistors. Each array on the S-Ram is 364 megabytes. It's on track for production, second half 11 continuing our two-year cadence. At Intel Moore's law is alive and well.
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