3D Network-on-Chip With On-Chip DRAM: An Empirical Analysis for Future Chip Multiprocessor
Source: Institute of Electrical and Electronics Engineers
With the increasing number of on-chip components and the critical requirement for processing power, Chip MultiProcessor (CMP) has gained wide acceptance in both academia and industry during the last decade. However, the conventional bus-based onchip communication schemes suffer from very high communication delay and low scalability in large scale systems. Network-on-Chip (NoC) has been proposed to solve the bottleneck of parallel onchip communications by applying different network topologies which separate the communication phase from the computation phase.
| Format: | Size: | 379.80 | |
| Date: | Nov 2010 |
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