40-nm FPGA Power Management and Advantages
The 40-nm process offers clear benefits over prior nodes, including the 65-nm node and the more recent 45-nm node. One of the most attractive benefits is higher integration, which enables semiconductor manufacturers to pack greater functionality into less physical space at lower costs. Although increased density and performance are valuable benefits, one of the most pressing design considerations for today's system developers is power consumption. To reduce power consumption, processing techniques go only so far. Smaller geometries provide the added benefit of reduced dynamic power consumption (less parasitic capacitances) but also raise standby power (increased leakage currents) unacceptably if no steps are taken to reduce it. Altera recognized this issue of increased power consumption and took aggressive steps to reduce both active and standby power.