A 1.1-Gb/s 115-PJ/bit Configurable MIMO Detector Using 0.13-m CMOS Technology

This brief presents an efficient and configurable Multiple-Input - Multiple-Output (MIMO) signal detector design solution and its high-speed IC implementation. This detector can support 2 � 2/3 � 3/4 � 4 MIMO and quadratic phase-shift keying/16-state Quadratic Amplitude Modulation (QAM)/64-state QAM modulation configurations. The detection algorithm employs an early-pruned technique that can reduce up to 46% node extensions in the K-Best sphere decoder while maintaining an almost maximum-likelihood performance. A parallel multistage folded very large scale integration architecture is accordingly developed that can achieve high detection throughput and configurability.