A 12.5-Gbps, 7-Bit Transmit DAC With 4-Tap LUT-Based Equalization in 0.13ìm CMOS

Random and systematic parameter fluctuations can degrade circuit performance and signal integrity in high-speed transmitters. For example, when multiphase clocks are used for data serialization, uneven clock phase spacing due to random and systematic variations can lead to inter-symbol timing mismatch. Also, DAC current mismatch introduces nonlinear characteristics to the transmitter output that cannot be easily addressed with conventional linear equalization techniques. As transmitter jitter is amplified by channel bandwidth limitations, especially at high data rates, inter symbol timing mismatch can further degrade performance.