A Flexible Heterogeneous Multi-Core Architecture

Multi-core processors naturally exploit Thread-Level Parallelism (TLP). However, extracting Instruction-Level Parallelism (ILP) from individual applications or threads is still a challenge as application mixes in this environment are non-uniform. Thus, multi-core processors should be flexible enough to provide high throughput for uniform parallel applications as well as high performance for more general workloads. Heterogeneous architectures are a first step in this direction, but partitioning remains static and only roughly fit application requirements. This paper proposes the Flexible Heterogeneous MultiCore processor (FMC), the first dynamic heterogeneous multi-core architecture capable of reconfiguring itself to fit application requirements without programmer intervention.