A Heterogeneous Network-on-Chip Architecture for Scalability and Service Guarantees
Source: International Journal of Advanced Research in Computer Science and Software Engineering (IJARCSSE)
Today's Chip-level Multi-Processors (CMPs) feature up to a hundred discrete cores, and with increasing levels of integration, CMPs with hundreds of cores, cache tiles, and specialized accelerators are anticipated in the near future. In this paper, the authors propose and evaluate technologies to enable Networks-On-Chip (NOCs) to support a thousand connected components (Kilo-NOC) with high area and energy efficiency, good performance, and strong Quality-of-Service (QOS) guarantees. Their analysis shows that QOS support burdens the network with high area and energy costs. In response, they propose a new light weight topology-aware QOS architecture that provides service guarantees for applications such as consolidated servers on CMPs and real-time SOCs.