A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design
Nowadays, multi-core Systems-on-Chip (SoCs) are typically required to execute multiple complex applications, which demand a large set of heterogeneous hardware cores with different sizes. In this context, the popularity of dynamically reconfigurable platforms (e.g., FPGAs) is growing, as they increase the ability of the initial design to adapt to future modifications. This paper presents a design flow to efficiently map multiple multi-core applications on a dynamically reconfigurable SoC. The proposed methodology is tailored for a reconfigurable hardware architecture based on a flexible communication infrastructure, and exploits applications similarities to obtain an effective mapping. The authors also introduce a run-time mapper that is able to introduce new applications that were not known at design-time, preserving the mapping of the original system.