A Multi-Core Sphere Decoder VLSI Architecture for MIMO Communications

The sphere decoding algorithm finds applications in Multi-Input Multi-Output (MIMO) decoding, because it achieves near Maximum Likelihood (ML) detection performance with significantly reduced computational complexity. Previous work has focused on implementations based on K-best or depth-first search, limiting the BER performance or the search speed. This paper presents a scalable multi-core sphere decoder architecture that can combine the advantages of the K-best and depth-first search methods. The proposed architecture demonstrated a 3-5 dB improvement in the BER performance for 16×16 systems using 16 Processing Elements (PEs) compared to the architecture with one PE. An improved search speed of the multi-core architecture also enables a 10× energy efficiency improvement over the single core architecture for the same data rate.