A Novel Methodology for Exploring Interconnection Architectures Targeting 3-D FPGAs
In current reconfigurable architectures the interconnection structures increasingly contribute more to the delay and power consumption. The demand for increased clock frequencies and logic density (smaller area footprint) makes the problem even more important. Three-Dimensional (3-D) integration can alleviate these problems by vertically stacking multiple physical layers. In this paper, the authors propose a methodology to evaluate different 3-D fabrication technologies and investigate heterogeneous interconnection schemes for 3-D FPGAs. In order to support this exploration methodology, a number of new tools were developed. Application of the proposed methodology on benchmark circuits demonstrates significant improvement in delay, power consumption, and total wire-length as compared to 2-D FPGAs.