A Novel Screen-Ability Estimation Methodology for DRAM With a Test Algorithm Simulator: FS5

In commodity Dynamic Random Access Memories (DRAMs), many kinds of test algorithms are evaluated to guarantee the quality and the yield of mass production test processes such as wafer level test, package level test, and module level test. Traditionally, comparing the yield of each test process has been the only way to evaluate test algorithms' screen-ability for each test process. Some previous studies on fault-coverage of test algorithms have focused on only the sequences of test algorithms and data topologies.