A Parameterizable Processor Architecture for Large Characteristic Pairing-Based Cryptography

Cryptographic pairing (bilinear mapping) is a core algorithm for various cryptography protocols. It is computationally expensive and inefficiently computed with general purpose processors. Although, there has been previous work looking into efficient hardware designs for pairing, most of these systems use small characteristic curves which are incompatible with practical software designs. In this paper, the authors propose a novel processor architecture for pairing-based cryptography applications using large characteristic curves. The architecture is parameterizable to fields with different bit-widths and different pairing algorithms.