A PIM (Processor-in-Memory) for Computer Graphics: Data Partitioning and Placement Schemes

The demand for higher performance graphics continues to grow because of the incessant desire towards realism. And, rapid advances in fabrication technology have enabled one to build several processor cores on a single die. Hence, it is important to develop single chip parallel architectures for such data-intensive applications. In this paper, the authors propose an efficient PIM architectures tailored for computer graphics which requires a large number of memory accesses. They then address the two important tasks necessary for maximally exploiting the parallelism provided by the architecture, namely, partitioning and placement of graphic data, which affect respectively load balances and communication costs. Under the constraints of uniform partitioning, they develop approaches for optimal partitioning and placement, which significantly reduce search space.