A Programmable, Scalable-Throughput Interleaver

The inter-leaver stages of digital communication standards show a surprisingly large variation in throughput, state sizes, and permutation functions. Furthermore, data rates for 4G standards such as LTE-Advanced will exceed typical baseband clock frequencies of handheld devices. Multi-stream operation for Software Defined Radio and iterative decoding algorithms will call for ever higher interleaves data rates. The authors' interleave machine is built around 8 single-port SRAM banks and can be programmed to generate up to 8 addresses every clock cycle.