A Statistical Approach to Contention Modeling for High-Level Heterogeneous Multiprocessor Simulation
Source: Carnegie Mellon University
Single chip systems featuring multiple heterogeneous processors and a variety of communication and memory architectures have emerged to satisfy the demand for networking, handheld computing, and other custom devices. The complex interactions between applications, schedulers, and processor resources, along with the resulting contention delays for shared busses and memories, are the chief limitation against raising the modeling abstraction level above the clock cycle. Without raising the simulation abstraction level, multiprocessor simulations are slow to build and execute, severely limiting the number of design iterations that can be considered, thus restricting the design space that can be explored.