Activity and Register Placement Aware Gated Clock Network Design
Clock gating is one of the most effective techniques to reduce clock network power dissipation. Although it has already been studied considerably, most of the previous works are restricted to either logic level or clock routing stage. Due to the restriction, clock gating often meets the trouble of wire-length overhead and frequent control signal switching, both of which degrade its effectiveness. Furthermore, previous de-sign flows which insert gate logics after placement introduce a lot of overlaps, especially when there are lots of gate logics inserted.