An Advanced BIRA Using Parallel Sub-Analyzers for Embedded Memories

Although many Built-In Redundancy Analysis (BIRA) algorithms which use parallel sub-analyzers have optimal repair rate and a fast analysis speed, they suffer from a large area overhead. To reduce the area overhead, a new BIRA analyzer is proposed which reconstructs the Content Addressable Memory (CAM) structure of the parallel sub-analyzers like a binary searching tree. Experimental results show that the proposed BIRA analyzer achieves 25% reduction of area overhead compared with previous BIRA using parallel sub-analyzers in case an embedded memory has 4 spares with optimal repair rate and zero analysis speed.