An Area-Efficient Built-in Redundancy Analysis for Embedded Memories With Optimal Repair Rate Using 2-D Redundancy
A novel Built-In Redundancy Analysis (BIRA) is proposed for embedded memories. The proposed BIRA algorithm has two phases. In the first phase, detected faults are collected to area-efficient fault storing Content Addressable Memory (CAM). In order to determine a correct repair solution, spare memories are allocated in the second phase using Linear Feedback Shift Register (LFSR) with fast analyzing speed. Experimental results show that the proposed BIRA algorithm achieves optimal repair rate and very low area overhead.