An Efficient Architecture for a TCP Offload Engine Based on Hardware/Software Co-Design
Source: Pusan National University
To achieve both the flexibility of software and the performance of hardware, the authors design a hybrid architecture for a TCP offload engine that is based on hardware/software co-design. In this architecture, the transmission and reception paths of TCP/IP are completely separated with the aid of two general embedded processors to process data transmission and reception simultaneously. They implement this architecture based on an FPGA that has two general embedded processor cores. In the experiments based on the gigabit Ethernet, the hybrid TOE has a minimum latency of 13.5 Î¼s. The CPU utilization is less than 3%, which is at least eighteen times lower than that of the general gigabit Ethernet adapters.