An Efficient BIST Architecture for Embedded RAMs
In this paper, a new BIST(Built-In Self-Test) structure for efficient test of embedded RAMs is proposed. In proposed Embedded Memory BIST(EMBIST) architecture, various algorithms are allowed to be executed, and just one controller can test more than one embedded memories. And, the proposed EMBIST has efficient structure that requires smaller hardware overhead. The experimental result demonstrates the effectiveness of proposed EMBIST architecture. As current System-On-Chip(SOC) designs become memory intensive, the manufacturing yield of such devices greatly depends on the yield of embedded memories.