An Efficient Low Power VLSI Architecture for Viterbi Decoder Using Null Convention Logic
Source: Kongu Engineering College
In 3G mobile terminals the Viterbi decoder consumes approximately one third of the power consumption of a base band mobile transceiver. Viterbi decoders employed in digital wireless communications are complex and dissipate large power. In this paper, to reduce the power consumption, and to increase the speed, an asynchronous technique that is delay insensitive Null Convention Logic (NCL) for Viterbi decoder using dual rail signal is proposed. NCL reduces the dynamic power consumption in terms of reducing the switching activity and also it reduces the glitch power significantly, thereby achieving the lower power.