Application-Aware NoC Design for Efficient SDRAM Access

In many-core processors based on Networks-on-Chip (NoC), memory Quality-of-Service (QoS) becomes one of the most important issues since both memory and on-chip network are critical shared resources. However, the improvement of memory performance aided by a memory subsystem independently working with an on-chip network is severely limited. Therefore, memory-aware NoC design has attracted great attentions. Many researchers have developed various QoS approaches for NoC.