BENoC: A Bus-Enhanced Network on-Chip

Recent research has shown that Network on-Chip (NoC) is superior to a bus in terms of power and area for given traffic throughput requirements. Consequently, NoC is expected to be the main interconnect infrastructure in future System on Chip (SoC) and Chip Multi-Processor (CMP). Unlike off-chip networks, VLSI modules are only a few millimeters apart, hence the cost of off-network communication among the network end-points and routers is quite low. Such off-network communication can circumvent weaknesses of the NoC, such as latency of critical signals, complexity and cost of broadcast operations, and operations requiring global knowledge or central control.