Cache-Aware Utilization Control for Energy Efficiency in Multi-Core Real-Time Systems

Multi-core processors are anticipated to become a major development platform for real-time systems. However, existing power management algorithms are not designed to sufficiently utilize the features available in many multi-core processors, such as shared L2 caches and per-core DVFS, to effectively minimize processor energy consumption while providing real-time guarantees. In this paper, the authors propose a two level utilization control solution for energy efficiency in multicore real-time systems. At the core level, the solution addresses two optimization objectives: Controlling the CPU utilization of each core to its desired schedulable bound and minimizing the core energy consumption by adopting per-core DVFS and dynamic L2 cache partitioning to adapt both the CPU frequency dependent and independent portions of the task execution times of the core.