Classifying Application Phases in Asymmetric Chip Multiprocessors

In present study, in order to improve the performance and reduce the amount of power which is dissipated in heterogeneous multi-core processors, the ability of detecting the program execution phases is investigated. The program's execution intervals have been classified in different phases based on their throughput and the utilization of the cores. The results of implementing the phase detection technique are investigated on a single core processor and also on a multi-core processor. To minimize the profiling overhead, an algorithm for the dynamic adjustment of the profiling intervals is presented. It is based on the behavior of the program and reduces the profiling overhead more than three-fold.