Compilation and Worst-Case Reaction Time Analysis for Multi Threaded Esterel Processing
Source: Hindawi Publishing
The recently proposed reactive processing architectures are characterized by Instruction Set Architectures (ISAs) that directly support reactive control flow including concurrency and preemption. These architectures provide efficient execution platforms for reactive synchronous programs; however, they do require novel compiler technologies, notably with respect to the handling of concurrency. Another key quality of the reactive architectures is that they have very predictable timing properties, which make it feasible to analyze their Worst-Case Reaction Time (WCRT). The authors present an approach to compile programs written in the synchronous language Esterel onto a reactive processing architecture that handles concurrency via priority-based multithreading.