Continuous-Time Sigma-Delta ADC in 1.2-V 90-Nm CMOS With 61-DB Peak SNDR and 74-DB Dynamic Range in 10-MHz Bandwidth

This paper describes a Continuous-Time Sigma-Delta (CTSD) analogue-to-digital converter (ADC) with 14-bit resolution, and a full-scale input 011.0 V p-p differential. The circuit is implemented in an 8-layer 90-nm 1.2-V CMOS process. Integrated into the macro is a low-jitter clock generator (LC-PLL). The macro is configurable to allow various oversampling ratios and signal bandwidths, which makes it suitable for multi-band applications such as WiMAX. The CTSD ADC provides the advantage of low power, requires no anti-aliasing filter, and is immune to noise outside the ADC bandwidth. The CTSD architecture uses a third-order single-loop sigma-delta with a 4-bit quantiser. Continuous background calibration is used to tune the quantiser thresholds and Digital-To-Analogue Converter (DAC) currents.