Design and Implementation of Custom Processor Architecture for Turbo Encoder and Decoder Using NISC
Turbo codes are a recently discovered class of error correction codes that achieve near-shannon limit performance. Because of their complexity and highly parallel nature, turbo coded applications are well suited for configurable computing. Field-Programmable Gate Arrays (FPGAs), which are the main building blocks of Configurable Computing Machines (CCMs), allow users to design flexible hardware that is optimized for performance, speed, power consumption, and chip-area. This paper aims to design and implement custom processor architecture for turbo encoder and decoder using NISC technology. They developed four different custom processor architectures and compared their performance in terms of speed, power and throughput by using NISC tool for different standards.