Design and Performance Analysis of 5 GHz CMOS RF Front-End Circuits for IEEE 802.11 a Application

Today the trend of RF CMOS analog design is technology scaling, which moving towards the deep submicron process to achieve improvement in power consumption, speed and chip area. The most severe consequence of technology scaling is reduction of the supply voltage. Therefore, the need for low voltage operating RF circuits with higher performance /lower price ratio has led to increase the interest and research of the front-end receiver. The aim of this paper is to design and analyze the performance of CMOS RF front-end circuits at low supply voltage.