Design and VLSI Implementation of 8 Mb Low Power SRAM in 90nm
This paper deals with the design and analysis of 8Mb Static Random Access Memory (SRAM) at 90nm, focusing on optimizing power and delay. The SRAM access path is split into two portions: from address input to word line rise (the row decoder) and from word line rise to data output (the read data path). Techniques to optimize both of these paths are investigated and implemented. In this paper, the existing SRAM architectures are investigated, and then a basic 6T SRAM structure was chosen. The decoder, excluding the pre-decoder, which constitutes the path from address input to the word line rise, is implemented as a binary structure by implementing a multi-stage path.