Design-Space Exploration for CMOS Photonic Processor Networks
Source: Boston University
This paper presents a review of recent advances in building high-throughput, energy-efficient photonic networks for core-to-core and core-to-DRAM communication in many-core processor systems. To sustain the performance scaling in these systems, the increase in core count has to be followed by the corresponding increase in energy-efficiency of the core, the interconnect, and bandwidth density. Due to pin-density, wire-bandwidth and power dissipation limits, electrical DRAM interfaces are not expected to supply sufficient bandwidth with reasonable power consumption and packaging cost, and similar issues also limit energy-efficiency and bandwidth density of global on-chip wires.