Designing a WISHBONE Protocol Network Adapter for an Asynchronous Network-on-Chip

The Scaling of microchip technologies, from micron to sub-micron and now to Deep Sub-Micron (DSM) range, has enabled large scale Systems-on-Chip (SoC). In future Deep Sub-Micron (DSM) designs, the interconnect effect will definitely dominate performance. Network-on-Chip (NoC) has become a promising solution to bus-based communication infrastructure limitations. NoC designs usually targets Application Specific Integrated Circuits (ASICs), however, the fabrication process costs a lot. Implementing a NoC on an FPGA does not only reduce the cost but also decreases programming and verification cycles. In this paper, an Asynchronous NoC has been implemented on a SPARTAN-3E device.