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asics - chip sets
(383 results)-
Whitepapers
Intel brings new experiences to life via Cloud Computing
Dec 2011
It seems that today's cloud technology is constantly pushing the envelope of what is or isn't possible in computing. Something as simple as putting a few letters into a search engine and getting...
Provided by Intel Corporation
-
Whitepapers
Intel IT Executive Insights: Intel IT's Cloud Computing Strategy
Jan 2012
Cloud computing is only growing and innovating and at Intel, it's one of their top 3 IT objectives for 2012. The idea of a virtualized data center is changing the way Intel looks at its...
Provided by Intel Corporation
-
White Papers
Designing a WISHBONE Protocol Network Adapter for an Asynchronous Network-on-Chip
Jul 2011
The Scaling of microchip technologies, from micron to sub-micron and now to Deep Sub-Micron (DSM) range, has enabled large scale Systems-on-Chip (SoC). In future Deep Sub-Micron (DSM) designs, the...
Provided by International Journal of Computer Science Issues
-
White Papers
Ant Colony Based Approach for Solving FPGA Routing
Jul 2011
This paper is based on an ant colony optimization algorithm (ASDR) for solving FPGA routing for a route based routing constraint model in FPGA design architecture. In this approach FPGA routing...
Provided by International Journal of Computer Science Issues
-
Whitepapers - Video
Securing the Cloud with Intel Trusted Execution Technology Usage Models
Jun 2011
Intel's Sr. Security Engineer, James Greene talks about usage models around trusted compute pools, secure on-boarding of virtual machines to a cloud environment and auditing of the security...
Provided by Intel Corporation
-
White Papers
Input Vector Control for Post-Silicon Leakage Current Minimization in the Presence of Manufacturing Variability
Jun 2008
The authors present the first approach for post-silicon leakage power reduction through Input Vector Control (IVC) that takes into account the impact of the Manufacturing Variability (MV). Because...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Trusted Integrated Circuits: A Nondestructive Hidden Characteristics Extraction Approach
Oct 2008
The authors have developed a methodology for unique identification of Integrated Circuits (ICs) that addresses untrusted fabrication and other security problems. The new method leverages...
Provided by Springer Science+Business Media
-
White Papers
Leakage Minimization Using Self Sensing and Thermal Management
Aug 2010
The authors have developed a system architecture, measuring and modeling techniques, and algorithms for on-line power and energy optimization and thermal management. The starting point for their...
Provided by Association for Computing Machinery
-
White Papers
A Gate Level Sensor Network for Integrated Circuits Temperature Monitoring
Jan 2011
The authors present the first sensor network architecture to monitor Integrated Circuits (IC) thermal and energy activity. The sensor network consists of a set of simple gates, which are...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Integrated Circuit Security Techniques Using Variable Supply Voltage
Jun 2011
This paper addresses Integrated Circuit (IC) security issues by using supply voltage based Gate-Level Characterization (GLC). The authors' GLC scheme is capable of characterizing both...
Provided by Association for Computing Machinery
-
White Papers
Integrated Circuit Digital Rights Management Techniques Using Physical Level Characterization
Oct 2011
Digital Rights Management (DRM) of Integrated Circuits (ICs) is a crucially important task both economically and strategically. Several IC metering techniques have been proposed, but until now...
Provided by Association for Computing Machinery
-
White Papers
Robust Passive Hardware Metering
Sep 2011
Current hardware metering techniques, which use manifestational properties of gates for ID extraction, are weakened by the non-uniform effects of aging in conjunction with variations in...
Provided by University of California
-
White Papers
Securing Netlist-Level FPGA Design Through Exploiting Process Variation and Degradation
Feb 2011
The continuously widening gap between the Non-Recurring Engineering (NRE) and Recurring Engineering (RE) costs of producing Integrated Circuit (IC) products in the past few decades gives high...
Provided by University of California
-
White Papers
CORDIC Algorithm Implementation in FPGA for Computation of Sine & Cosine Signals
Dec 2011
Many hardware algorithms exist to handle the hardware intensive signal processing problems. Among these algorithms is a set of shift-add algorithms collectively known as CORDIC for computing a...
Provided by International Journal of Scientific & Engineering Research
-
White Papers
3-D Camera SoPC Design Architecture
Nov 2011
It is often seen that the available knowledge base within an organisation influences the selection of the design platform. The two major contenders for signal processing hardware platforms are DSP...
Provided by International Journal of Scientific & Engineering Research
-
White Papers
Implementation of Generic Algorithm Using VHDL on FPGA
Sep 2011
The development of a flexible Very-Large-Scale Integration (VLSI) for GA has been proposed in this paper. For the hardware architecture, the authors have develop on a Random Number Generator...
Provided by International Journal of Scientific & Engineering Research
-
White Papers
A New Method for Designing QCA Circuits
Jan 2012
In this paper, the authors tried to solve some of the problems in logical designing based on Quantum-dot Cellular Automata (QCA) technology especially by using Null Convention Logic (NCL) instead...
Provided by International Association of Computer Science & Information Technology (IACSIT)
-
White Papers
An Analytical Model Relating FPGA Architecture to Logic Density and Depth
Sep 2010
This paper presents an analytical model that relates FPGA architectural parameters to the logic size and depth of an FPGA implementation. In particular, the model relates the lookup-table size,...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
An Energy and Power Consumption Analysis of FPGA Routing Architectures
Aug 2009
In this paper, the authors evaluate bi-directional and unidirectional FPGA routing architectures in terms of energy and power consumption using an updated power estimation framework compatible...
Provided by Miami University of Ohio
-
White Papers
Modeling Post-Techmapping and Post-Clustering FPGA Circuit Depth
Jun 2009
This paper presents an analytical model that relates FPGA architectural parameters to the expected speed of FPGA implementation. More precisely, the model relates the lookup-table size, cluster...
Provided by University of British Columbia
-
White Papers
Wirelength Modeling for Homogeneous and Heterogeneous FPGA Architectural Development
Feb 2009
This paper describes an analytical model that relates the architectural parameters of an FPGA to the average pre-routing wire-length of an FPGA implementation. Both homogeneous and heterogeneous...
Provided by Association for Computing Machinery
-
White Papers
An Analytical Model Describing the Relationships Between Logic Architecture and FPGA Density
Jun 2008
This paper describes an analytical model, based principally on Rent's Rule, that relates logic architectural parameters to the area efficiency of an FPGA. In particular, the model relates the...
Provided by University of British Columbia
-
White Papers
Static and Dynamic Memory Footprint Reduction for FPGA Routing Algorithms
Jan 2009
During routing, memory is required to store both architectural data and temporary routing data. The architectural data is static, and provides a representation of the physical routing resources...
Provided by Association for Computing Machinery
-
White Papers
A System-Level Stochastic Circuit Generator for FPGA Architecture Evaluation
Sep 2008
The authors describe a stochastic circuit generator that can be used to automatically create benchmark circuits for use in FPGA architecture studies. The circuits consist of a hierarchy of...
Provided by University of British Columbia
-
White Papers
Memory Footprint Reduction for FPGA Routing Algorithms
Jan 2008
In this paper, the authors present a technique to reduce the run-time memory footprint of FPGA routing algorithms. These algorithms require a representation of the physical routing resources and...
Provided by University of British Columbia
-
White Papers
On the Tradeoff Between Power and Flexibility of FPGA Clock Networks
May 2008
FPGA clock networks consume a significant amount of power since they toggle every clock cycle and must be flexible enough to implement the clocks for a wide range of different applications. The...
Provided by Association for Computing Machinery
-
White Papers
GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering
Dec 2007
This paper describes Glitchless, a circuit-level technique for reducing power in FPGAs by eliminating unnecessary logic transitions called glitches. This is done by adding programmable delay...
Provided by University of British Columbia
-
White Papers
Floating-Point FPGA: Architecture and Modeling
Dec 2009
This paper presents an architecture for a reconfigurable device that is specifically optimized for floating-point applications. Fine-grained units are used for implementing control logic and...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Simultaneous PVT-Tolerant Voltage-Island Formation and Core Placement for Thousand-Core Platforms
Jul 2009
In this paper, the authors propose a novel approach to voltage island formation and core placement for energy optimization in many-core architectures under parameter variations at pre-fabrication...
Provided by University of British Columbia
-
White Papers
Charge-Borrowing Decap: A Novel Circuit for Removal of Local Supply Noise Violations
Apr 2009
The authors propose a novel circuit called Charge-Borrowing Decap (CBD) as a drop-in replacement for passive decaps to reduce supply noise for removal of "Hot-spot" IR-drop problems found late in...
Provided by University of British Columbia
-
White Papers
Low-Cost Hardware Profiling of Run-Time and Energy in FPGA Embedded Processors
Jun 2011
Field-Programmable Gate Arrays (FPGAs) are a widely used technology in the design of embedded systems due to their improving speed, density and power, steadily decreasing cost, and their...
Provided by University of Toronto
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White Papers
Latch-Based Performance Optimization for FPGAs
Jun 2011
The authors explore using pulsed latches for timing optimization - a first in the FPGA community. Pulsed latches are transparent latches driven by a clock with a non-standard (non-50%) duty cycle....
Provided by University of Toronto
-
White Papers
Reducing FPGA Router Run-Time Through Algorithm and Architecture
Jun 2011
The authors propose a new FPGA routing approach that, when combined with a low-cost architecture change, results in a 34% reduction in router run-time, at the cost of a 3% area overhead, with no...
Provided by University of Toronto
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White Papers
Architecture Description and Packing for Logic Blocks With Hierarchy, Modes and Complex Interconnect
Mar 2011
The development of future FPGA fabrics with more sophisticated and complex logic blocks requires a new CAD flow that permits the expression of that complexity and the ability to synthesize to it....
Provided by Association for Computing Machinery
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White Papers
Area-Efficient FPGA Logic Elements: Architecture and Synthesis
Nov 2010
The authors consider architecture and synthesis techniques for FPGA logic elements (function generators) and show that the LUT-based logic elements in modern commercial FPGAs are over-engineered....
Provided by University of Toronto
-
White Papers
Process Induced Random Variation Models of Nanoscale MOS Performance: Efficient Tool for the Nanoscale Regime Analog/mixed Signal CMOS Statistical/variability Aware Design
Jan 2012
In this paper, the novel models of random variation in Ids which is a key parameter of any MOS transistor, have been proposed in this paper as the probability density functions. Both triode and...
Provided by International Association of Computer Science & Information Technology (IACSIT)
-
White Papers
Modeling of Reliability for Programmable Nanowires Interconnect
Feb 2012
A Field-Programmable Nanowire Interconnect (FPNI) is from hybrid CMOS/nano circuit family, that generalizes CMOL (CMOS/molcular hybrid) proposed by Likharev, that reparieren technology for a...
Provided by International Association of Computer Science & Information Technology (IACSIT)
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White Papers
Design and Implementation of Vending Machine Using Verilog HDL
Jan 2012
The vending machines are used to dispenses small different products (snacks, ice creams, cold drinks etc.), when a coin is inserted. These machines can be implemented in different ways by using...
Provided by International Association of Computer Science & Information Technology (IACSIT)
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White Papers
A Decade of Productive FPGA Utilization With Genetic Algorithms
Jan 2012
Genetic algorithms are one of the best ways to deal with the optimization problems. They are precisely suitable for mixed combinatorial problems. As genetic algorithms find the solution by...
Provided by Journal of Theoretical and Applied Information Technology
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White Papers
Fault Detection and Test Minimization Methods for Combinational Circuits - A Survey
Dec 2011
Rapid increase in population increased the usage of digital components dramatically and their production. For profitable income, the cost of the finished product and time taken for marketing the...
Provided by Alagappa University
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Case Studies
Animation Gets an Energy-Efficient Upgrade
Mar 2010
Maya Entertainment faces the challenge to fulfill the demands to deliver larger, more complex film formats such as High Definition (HD) and stereoscopy, while utilizing the same space. Solution...
Provided by Intel
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White Papers
A full-Custom ASIC Design of a 8-bit, 25 MHz, Pipeline ADC Using 0.35 um CMOS technology
Nov 2010
The purpose of this project was to design and implement a pipeline Analog-to-Digital Converter using 0.35um CMOS technology. Initial requirements of a 25-MHz conversion rate and 8-bits of...
Provided by Chalmers University of Technology
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White Papers
Adaptive FPGA NoC-Based Architecture for Multispectral Image Correlation
Mar 2008
An adaptive FPGA architecture based on the NoC (Network-on-Chip) approach is used for the multispectral image correlation. This architecture must contain several distance algorithms depending on...
Provided by Cornell University
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White Papers
Sinusoidal Frequency Doublers Circuit With Low Voltage + 1. 5 Volt CMOS Inverter
Jan 2010
Sinusoidal frequency doublers are popular in telecommunication for example using instrument processing, or circuit analysis in analog processing. The normally, sinusoidal frequency doublers has be...
Provided by Kasem Bundit University
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White Papers
Classifying Application Phases in Asymmetric Chip Multiprocessors
Jan 2010
In present study, in order to improve the performance and reduce the amount of power which is dissipated in heterogeneous multi-core processors, the ability of detecting the program execution...
Provided by Iran University of Science and Technology
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White Papers
A Damq Shared Buffer Scheme for Network-on-Chip
Jul 2007
In this paper the authors present a novel shared buffer scheme for network on chip applications. The proposed scheme is based on a dynamically allocated multi queue self-compacting buffer. Two...
Provided by Washington State University
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White Papers
Energy Efficient Packet Classification Hardware Accelerator
Mar 2008
Packet classification is an important function in a router's line-card. Although many excellent solutions have been proposed in the past, implementing high speed packet classification reaching up...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
FROCM: A Fair and Low-Overhead Method in SMT Processor
Sep 2007
Simultaneous Multithreading (SMT) and Chip Multiprocessors (CMP) processors have emerged as the mainstream computing platform in major market segments, including PC, server, and embedded domains....
Provided by Springer Science+Business Media
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White Papers
A Low-Power Globally Synchronous Locally Asynchronous FFT Processor
Sep 2007
Low-power design became crucial with the widespread use of the embedded systems, where a small battery has to last for a long period. The embedded processors need to efficient in order to achieve...
Provided by Springer Science+Business Media
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White Papers
Adaptive Power Control With Online Model Estimation for Chip Multiprocessors
Oct 2010
As Chip Multiprocessors (CMPs) become the main trend in processor development, various power and thermal management strategies have recently been proposed to optimize system performance while...
Provided by University of Tennessee
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White Papers
Temperature-Constrained Power Control for Chip Multiprocessors With Online Model Estimation
Jun 2009
As Chip Multiprocessors (CMPs) become the main trend in processor development, various power and thermal management strategies have recently been proposed to optimize system performance while...
Provided by Association for Computing Machinery
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White Papers
Achieving Fair or Differentiated Cache Sharing in Power-Constrained Chip Multiprocessors
Sep 2009
Limiting the peak power consumption of Chip Multi Processors (CMPs) has recently received a lot of attention. In order to enable chip-level power capping, the peak power consumption of on-chip L2...
Provided by University of Tennessee
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White Papers
OCP-IP Network-on-Chip Benchmarking Workgroup
Dec 2010
This article presents a summary of the work and infrastructure developed by the OCP-IP Network-on-Chip benchmarking workgroup. Network-on-chip (NoC) is an emerging paradigm for interconnecting...
Provided by Tampere University of Technology
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White Papers
Low Power Gated Bus Synthesis Using Shortest-Path Steiner Graph for System-on-Chip Communications
Jul 2009
Power consumption of system-level on-chip communications is becoming more significant in the overall System-On-Chip (SoC) power as technology scales down. In this paper, the authors propose a low...
Provided by Association for Computing Machinery
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White Papers
Designing Secure Systems on Reconfigurable Hardware
Jul 2008
The extremely high cost of custom ASIC fabrication makes FPGAs an attractive alternative for deployment of custom hardware. Embedded systems based on reconfigurable hardware integrate many...
Provided by Association for Computing Machinery
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White Papers
ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors
Nov 2008
This paper proposes and studies a hardware-based adaptive controlled migration strategy for managing distributed L2 caches in chip multiprocessors. Building on an area-efficient shared cache...
Provided by Springer Science+Business Media
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White Papers
StimulusCache: Boosting Performance of Chip Multiprocessors With Excess Cache
Jan 2010
Technology advances continuously shrink on-chip devices. Consequently, the number of cores in a single Chip Multiprocessor (CMP) is expected to grow in coming years. Unfortunately, with smaller...
Provided by University of Pittsburgh
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Whitepapers
An XML-Based Collaborative Framework for ASIC EDesign
Jan 2010
Efficient management of the large number of expertise and services required for design and verification of complex integrated circuits demands a collaborative design environment. Such an...
Provided by IBM
-
White Papers
Intel® Atom™ Developer Program Celebrates One Year with New Name and More
Oct 2010
With its one-year anniversary, the Intel Atom® Developer™ Program has unveiled a new name: the Intel AppUpSM developer program. In addition, app developers can now download the new gold-release...
Provided by Intel Corporation
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White Papers
FPGA Power Management and Modeling Techniques
Nov 2007
As designs get larger and add more system functions implemented on FPGAs, and as the advanced silicon process technology moves into smaller geometries, power consumption is increasingly a concern...
Provided by Altera
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White Papers
Floating-Point Compiler: Increasing Performance With Fewer Resources
Nov 2007
Showing new levels of high-performance, high-density, IEEE754-compliant floating-point applications in FPGAs is the focus of this white paper. A new tool is introduced that will allow 100 percent...
Provided by Altera
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White Papers
Performing Equivalent Timing Analysis Between Altera TimeQuest and Xilinx Trace
Nov 2007
Most hardware designers who are qualifying FPGA performance normally run software benchmark comparisons of FPGAs from different vendors to determine which vendor provides the largest margin for...
Provided by Altera
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White Papers
Basic Principles of Signal Integrity
Dec 2007
Digital designs have not traditionally suffered by issues associated with transmission line effects. At lower frequencies the signals remain within data characterization and the system performs as...
Provided by Altera
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White Papers
Electronic Warfare Design With PLDs and High-Speed Transceivers
Dec 2007
Electronic warfare has become part of the strategic landscape for all warfighters on the ground, at sea, and in the air. Threats change quickly, so fast characterization of the electromagnetic...
Provided by Altera
-
White Papers
Developing MSAN Equipment Using Low-Cost FPGAs
Jan 2008
This paper looks at the trends in the Multi-Service Access Node (MSAN) equipment market that are forcing developers to re-examine the architectures they have used in the past, as well as driving...
Provided by Altera
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White Papers
The Quest for Digital Broadcast Quality: Addressing Quality Hot Spots
Feb 2008
Digital signal processing within Digital Televisions (DTVs) has advanced significantly, resulting in improved picture and audio quality. Further improvements in DTV technology over the next...
Provided by Altera
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White Papers
Enabling New Infotainment-Equipment Cost Structures With Open-System Architectures
Feb 2008
The infotainment systems of Original Equipment Manufacturers (OEMs) recently have been subjected to increasing competition from the retrofitting solutions on the so-called aftermarket, for which...
Provided by Altera
-
White Papers
Using FPGA-Based Channel Bonding for HDTV Over DSL
Feb 2008
This white paper examines the market opportunities for channel bonding technology and the threat from fiber-based networks and protocol details of the channel bonding process, as well as...
Provided by Altera
-
White Papers
Increase Performance in Video and Image Processing Applications With FPGA Integration
Mar 2008
The JPEG2000 standard was developed to address a wide range of video and imaging applications, including medical imaging, military and security systems, and digital cinema. To enable these...
Provided by Altera
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White Papers
Increase Performance in Imaging Applications by Integrating DSP Functions With FPGAs
Mar 2008
Intevac is a leading developer of photonics products for commercial and military markets. This white paper describes the development of the embedded electronic systems for their NightVista...
Provided by Altera
-
White Papers
FPGA Run-Time Reconfiguration: Two Approaches
Mar 2008
Run-time reconfiguration for FPGA designs is an increasingly important requirement for many user markets, particularly military users who must adapt quickly to different threats and evolving...
Provided by Altera
-
White Papers
Supporting Unknown FREF Video Applications With PLLs
Mar 2008
Cyclone III Phase-Locked Loops (PLLs) are feature rich, supporting advanced capabilities such as clock switchover, dynamic phase shifting, and PLL reconfiguration. Previously, PLLs in Altera...
Provided by Altera
-
White Papers
Increasing Productivity With Quartus II Incremental Compilation
May 2008
Designers are creating FPGAs that continue to increase in logic density and performance, yet their time-to-market pressures are becoming even more demanding. Computing power is not increasing as...
Provided by Altera
-
White Papers
DPA Circuitry and rx_dpa_locked Signal Behavior in Stratix III Devices
Jun 2008
The receiver PLL provides eight clock phases to the DPA circuitry. The eight clock phases are separated by 45° and at a frequency equal to the serial data rate. After power up or reset, the DPA...
Provided by Altera
-
White Papers
Military Productivity Factors in Large FPGA Designs
Jul 2008
Changes in technology and requirements are leading to FPGAs playing larger roles in defense electronics designs, and consequently are creating both opportunities and risks. The opportunities...
Provided by Altera
-
White Papers
DO-254 Support for FPGA Design Flows
Jul 2008
For most defense engineers, the first time they hear about the DO-254 Design Assurance Standard is in a request from their customer beginning with the words "Thou shalt comply with?" This leaves...
Provided by Altera
-
White Papers
40-nm FPGAs and the Defense Electronic Design Organization
Jul 2008
With Altera's introduction of 40-nm FPGAs, the design domains of military electronics that can be addressed with Programmable Logic Devices (PLDs) are growing. This growth is a response to...
Provided by Altera
-
White Papers
Hardware/Software Co-Verification Using FPGA Platforms
Aug 2008
The problem of hardware and software co-design is as old as systems design and the integration of systems composed of multiple elements. Systems built using electrical and electronic subsystems,...
Provided by Altera
-
White Papers
Creating Low-Cost Intelligent Display Modules With an FPGA and Embedded Processor
Sep 2008
LCDs are fast becoming a standard part of the automotive interior. As demand for LCD technology increases, so do methodologies for controlling and creating the displayed graphical content....
Provided by Altera
-
White Papers
Applying Graphics to FPGA-Based Solutions
Sep 2008
Like it or not, the Apple iPhone has changed the game. Every device imaginable is getting a revamp with colorful displays and easy-to-use interfaces. Companies are racing frantically to be first...
Provided by Altera
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Whitepapers
Inside Intel IT on Cloud Computing and Security
Jan 2012
Certainly no one expects that a company like Intel doesn't have issues when it comes to computing in the cloud, they do by the way. The real question is, how do they handle them, what are Intel...
Provided by Intel Corporation
-
Whitepapers
Intel IT Executive Insights: Intel IT's Cloud Computing Strategy
Jan 2012
Cloud computing is only growing and innovating and at Intel, it's one of their top 3 IT objectives for 2012. The idea of a virtualized data center is changing the way Intel looks at its...
Provided by Intel Corporation
-
White Papers
Designing a WISHBONE Protocol Network Adapter for an Asynchronous Network-on-Chip
Jul 2011
The Scaling of microchip technologies, from micron to sub-micron and now to Deep Sub-Micron (DSM) range, has enabled large scale Systems-on-Chip (SoC). In future Deep Sub-Micron (DSM) designs, the...
Provided by International Journal of Computer Science Issues
-
White Papers
Ant Colony Based Approach for Solving FPGA Routing
Jul 2011
This paper is based on an ant colony optimization algorithm (ASDR) for solving FPGA routing for a route based routing constraint model in FPGA design architecture. In this approach FPGA routing...
Provided by International Journal of Computer Science Issues
-
Whitepapers - Video
Securing the Cloud with Intel Trusted Execution Technology Usage Models
Jun 2011
Intel's Sr. Security Engineer, James Greene talks about usage models around trusted compute pools, secure on-boarding of virtual machines to a cloud environment and auditing of the security...
Provided by Intel Corporation
-
White Papers
Input Vector Control for Post-Silicon Leakage Current Minimization in the Presence of Manufacturing Variability
Jun 2008
The authors present the first approach for post-silicon leakage power reduction through Input Vector Control (IVC) that takes into account the impact of the Manufacturing Variability (MV). Because...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Trusted Integrated Circuits: A Nondestructive Hidden Characteristics Extraction Approach
Oct 2008
The authors have developed a methodology for unique identification of Integrated Circuits (ICs) that addresses untrusted fabrication and other security problems. The new method leverages...
Provided by Springer Science+Business Media
-
White Papers
Leakage Minimization Using Self Sensing and Thermal Management
Aug 2010
The authors have developed a system architecture, measuring and modeling techniques, and algorithms for on-line power and energy optimization and thermal management. The starting point for their...
Provided by Association for Computing Machinery
-
White Papers
A Gate Level Sensor Network for Integrated Circuits Temperature Monitoring
Jan 2011
The authors present the first sensor network architecture to monitor Integrated Circuits (IC) thermal and energy activity. The sensor network consists of a set of simple gates, which are...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Integrated Circuit Security Techniques Using Variable Supply Voltage
Jun 2011
This paper addresses Integrated Circuit (IC) security issues by using supply voltage based Gate-Level Characterization (GLC). The authors' GLC scheme is capable of characterizing both...
Provided by Association for Computing Machinery
-
White Papers
Integrated Circuit Digital Rights Management Techniques Using Physical Level Characterization
Oct 2011
Digital Rights Management (DRM) of Integrated Circuits (ICs) is a crucially important task both economically and strategically. Several IC metering techniques have been proposed, but until now...
Provided by Association for Computing Machinery
-
White Papers
Robust Passive Hardware Metering
Sep 2011
Current hardware metering techniques, which use manifestational properties of gates for ID extraction, are weakened by the non-uniform effects of aging in conjunction with variations in...
Provided by University of California
-
White Papers
Securing Netlist-Level FPGA Design Through Exploiting Process Variation and Degradation
Feb 2011
The continuously widening gap between the Non-Recurring Engineering (NRE) and Recurring Engineering (RE) costs of producing Integrated Circuit (IC) products in the past few decades gives high...
Provided by University of California
-
White Papers
CORDIC Algorithm Implementation in FPGA for Computation of Sine & Cosine Signals
Dec 2011
Many hardware algorithms exist to handle the hardware intensive signal processing problems. Among these algorithms is a set of shift-add algorithms collectively known as CORDIC for computing a...
Provided by International Journal of Scientific & Engineering Research
-
White Papers
3-D Camera SoPC Design Architecture
Nov 2011
It is often seen that the available knowledge base within an organisation influences the selection of the design platform. The two major contenders for signal processing hardware platforms are DSP...
Provided by International Journal of Scientific & Engineering Research
-
White Papers
Implementation of Generic Algorithm Using VHDL on FPGA
Sep 2011
The development of a flexible Very-Large-Scale Integration (VLSI) for GA has been proposed in this paper. For the hardware architecture, the authors have develop on a Random Number Generator...
Provided by International Journal of Scientific & Engineering Research
-
White Papers
A New Method for Designing QCA Circuits
Jan 2012
In this paper, the authors tried to solve some of the problems in logical designing based on Quantum-dot Cellular Automata (QCA) technology especially by using Null Convention Logic (NCL) instead...
Provided by International Association of Computer Science & Information Technology (IACSIT)
-
White Papers
An Analytical Model Relating FPGA Architecture to Logic Density and Depth
Sep 2010
This paper presents an analytical model that relates FPGA architectural parameters to the logic size and depth of an FPGA implementation. In particular, the model relates the lookup-table size,...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
An Energy and Power Consumption Analysis of FPGA Routing Architectures
Aug 2009
In this paper, the authors evaluate bi-directional and unidirectional FPGA routing architectures in terms of energy and power consumption using an updated power estimation framework compatible...
Provided by Miami University of Ohio
-
White Papers
Modeling Post-Techmapping and Post-Clustering FPGA Circuit Depth
Jun 2009
This paper presents an analytical model that relates FPGA architectural parameters to the expected speed of FPGA implementation. More precisely, the model relates the lookup-table size, cluster...
Provided by University of British Columbia
-
White Papers
Wirelength Modeling for Homogeneous and Heterogeneous FPGA Architectural Development
Feb 2009
This paper describes an analytical model that relates the architectural parameters of an FPGA to the average pre-routing wire-length of an FPGA implementation. Both homogeneous and heterogeneous...
Provided by Association for Computing Machinery
-
White Papers
An Analytical Model Describing the Relationships Between Logic Architecture and FPGA Density
Jun 2008
This paper describes an analytical model, based principally on Rent's Rule, that relates logic architectural parameters to the area efficiency of an FPGA. In particular, the model relates the...
Provided by University of British Columbia
-
White Papers
Static and Dynamic Memory Footprint Reduction for FPGA Routing Algorithms
Jan 2009
During routing, memory is required to store both architectural data and temporary routing data. The architectural data is static, and provides a representation of the physical routing resources...
Provided by Association for Computing Machinery
-
White Papers
A System-Level Stochastic Circuit Generator for FPGA Architecture Evaluation
Sep 2008
The authors describe a stochastic circuit generator that can be used to automatically create benchmark circuits for use in FPGA architecture studies. The circuits consist of a hierarchy of...
Provided by University of British Columbia
-
White Papers
Memory Footprint Reduction for FPGA Routing Algorithms
Jan 2008
In this paper, the authors present a technique to reduce the run-time memory footprint of FPGA routing algorithms. These algorithms require a representation of the physical routing resources and...
Provided by University of British Columbia
-
White Papers
On the Tradeoff Between Power and Flexibility of FPGA Clock Networks
May 2008
FPGA clock networks consume a significant amount of power since they toggle every clock cycle and must be flexible enough to implement the clocks for a wide range of different applications. The...
Provided by Association for Computing Machinery
-
White Papers
GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering
Dec 2007
This paper describes Glitchless, a circuit-level technique for reducing power in FPGAs by eliminating unnecessary logic transitions called glitches. This is done by adding programmable delay...
Provided by University of British Columbia
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White Papers
Floating-Point FPGA: Architecture and Modeling
Dec 2009
This paper presents an architecture for a reconfigurable device that is specifically optimized for floating-point applications. Fine-grained units are used for implementing control logic and...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Simultaneous PVT-Tolerant Voltage-Island Formation and Core Placement for Thousand-Core Platforms
Jul 2009
In this paper, the authors propose a novel approach to voltage island formation and core placement for energy optimization in many-core architectures under parameter variations at pre-fabrication...
Provided by University of British Columbia
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White Papers
Charge-Borrowing Decap: A Novel Circuit for Removal of Local Supply Noise Violations
Apr 2009
The authors propose a novel circuit called Charge-Borrowing Decap (CBD) as a drop-in replacement for passive decaps to reduce supply noise for removal of "Hot-spot" IR-drop problems found late in...
Provided by University of British Columbia
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White Papers
Low-Cost Hardware Profiling of Run-Time and Energy in FPGA Embedded Processors
Jun 2011
Field-Programmable Gate Arrays (FPGAs) are a widely used technology in the design of embedded systems due to their improving speed, density and power, steadily decreasing cost, and their...
Provided by University of Toronto
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White Papers
Latch-Based Performance Optimization for FPGAs
Jun 2011
The authors explore using pulsed latches for timing optimization - a first in the FPGA community. Pulsed latches are transparent latches driven by a clock with a non-standard (non-50%) duty cycle....
Provided by University of Toronto
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White Papers
Reducing FPGA Router Run-Time Through Algorithm and Architecture
Jun 2011
The authors propose a new FPGA routing approach that, when combined with a low-cost architecture change, results in a 34% reduction in router run-time, at the cost of a 3% area overhead, with no...
Provided by University of Toronto
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White Papers
Architecture Description and Packing for Logic Blocks With Hierarchy, Modes and Complex Interconnect
Mar 2011
The development of future FPGA fabrics with more sophisticated and complex logic blocks requires a new CAD flow that permits the expression of that complexity and the ability to synthesize to it....
Provided by Association for Computing Machinery
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White Papers
Area-Efficient FPGA Logic Elements: Architecture and Synthesis
Nov 2010
The authors consider architecture and synthesis techniques for FPGA logic elements (function generators) and show that the LUT-based logic elements in modern commercial FPGAs are over-engineered....
Provided by University of Toronto
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White Papers
Process Induced Random Variation Models of Nanoscale MOS Performance: Efficient Tool for the Nanoscale Regime Analog/mixed Signal CMOS Statistical/variability Aware Design
Jan 2012
In this paper, the novel models of random variation in Ids which is a key parameter of any MOS transistor, have been proposed in this paper as the probability density functions. Both triode and...
Provided by International Association of Computer Science & Information Technology (IACSIT)
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White Papers
Modeling of Reliability for Programmable Nanowires Interconnect
Feb 2012
A Field-Programmable Nanowire Interconnect (FPNI) is from hybrid CMOS/nano circuit family, that generalizes CMOL (CMOS/molcular hybrid) proposed by Likharev, that reparieren technology for a...
Provided by International Association of Computer Science & Information Technology (IACSIT)
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White Papers
Design and Implementation of Vending Machine Using Verilog HDL
Jan 2012
The vending machines are used to dispenses small different products (snacks, ice creams, cold drinks etc.), when a coin is inserted. These machines can be implemented in different ways by using...
Provided by International Association of Computer Science & Information Technology (IACSIT)
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White Papers
A Decade of Productive FPGA Utilization With Genetic Algorithms
Jan 2012
Genetic algorithms are one of the best ways to deal with the optimization problems. They are precisely suitable for mixed combinatorial problems. As genetic algorithms find the solution by...
Provided by Journal of Theoretical and Applied Information Technology
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White Papers
Fault Detection and Test Minimization Methods for Combinational Circuits - A Survey
Dec 2011
Rapid increase in population increased the usage of digital components dramatically and their production. For profitable income, the cost of the finished product and time taken for marketing the...
Provided by Alagappa University
