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processors
(1927 results)-
White Papers
ATAC: On-Chip Optical Networks for Multicore Processors
Jul 2009
ˆe trend in modern microprocessor architectures is clear: multicore is here. As silicon resources become increasingly abundant, processor designers are able to place more and more cores on a...
Provided by Massachusetts Institute of Technology
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White Papers
Main Memory DBMS on Modern Processors, a Simulation Approach for Database Performance Characterization
Jan 2008
Database applications are an important type of workloads that is very different from other types of application workloads such as SPEC benchmarks. In the past, much research has been devoted to...
Provided by Indiana University
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White Papers
Multi Processors, Their Memory Organizations and Implementations by Intel & AMD
Nov 2008
Multi-core processors represent a major evolution in computing technology and are becoming very popular today. Multi-core processors will eventually become the pervasive computing model because...
Provided by Electronic Visualization Laboratory
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White Papers
Miss Reduction in Embedded Processors Through Dynamic, Power-Friendly Cache Design
Jun 2008
Today, embedded processors are expected to be able to run complex, algorithm-heavy applications that were originally designed and coded for general-purpose processors. As a result, traditional...
Provided by Association for Computing Machinery
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White Papers
Modeling Multigrain Parallelism on Heterogeneous Multi-Core Processors: A Case Study of the Cell BE
Nov 2007
Heterogeneous multi-core processors invest the most significant portion of their transistor budget in customized "Accelerator" cores, while using a small number of conventional low-end cores for...
Provided by Virginia Polytechnic Institute and State University
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White Papers
A Low Power CMOS CORDIC Processor Design for Wireless Telecommunication
May 2007
A CORDIC processor for wire telecommunication is integrated in a 0.5ìm CMOS technology. The CORDIC (Coordinate Rotation DIgital Computer) processor reduces the circuit complexity by performing a...
Provided by Northeastern University
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White Papers
Parallelization of the Multigrid Solver With Processor Virtualization
Jan 2011
Processor virtualization is a parallelization technique proposed to get rid of the limitation of physical processors, while exploring the natural parallelism of the application. The virtualization...
Provided by University of South Dakota
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White Papers
Intel Virtualization Technology FlexMigration Application Note
May 2010
Intel Virtualization Technology (Intel VT) refers to a suite of hardware assists in Intel silicon (the Processors, Chipsets and Networking Devices) that make virtualization software simpler and...
Provided by Intel
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White Papers
Intel Cloud Builder Guide to Cloud Design and Deployement on Intel Xeon Processor-Based Platforms
Apr 2010
Cloud computing offers a path to greater scalability and lower costs for service providers, infrastructure hosting companies, and large enterprises. Establishing an infrastructure that can provide...
Provided by Intel
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White Papers
StimulusCache: Boosting Performance of Chip Multiprocessors With Excess Cache
Jan 2010
Technology advances continuously shrink on-chip devices. Consequently, the number of cores in a single Chip Multiprocessor (CMP) is expected to grow in coming years. Unfortunately, with smaller...
Provided by University of Pittsburgh
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White Papers
ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors
Nov 2008
This paper proposes and studies a hardware-based adaptive controlled migration strategy for managing distributed L2 caches in chip multiprocessors. Building on an area-efficient shared cache...
Provided by Springer Science+Business Media
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White Papers
Piecemeal: A Formal Collaborative Editing Technique Guaranteeing Correctness
Mar 2010
While collaboration on documents has been supported for several decades by a variety of systems and tools, in recent months a renewed interest is apparent through the appearance of new...
Provided by University of Southern Queensland
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White Papers
Performance-Asymmetry-Aware Topology Virtualization for Defect-Tolerant NoC-Based Many-Core Processors
Feb 2010
Topology virtualization techniques are proposed for NoCbased many-core processors with core-level redundancy to isolate hardware changes caused by on-chip defective cores. Prior work focuses on...
Provided by Economic Development Association of Alabama
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White Papers
Leading Virtualization Performance and Energy Efficiency in a Multi-Processor Server
Nov 2008
With the architecture that's specifically built for virtualization, the Intel Xeon processor 7400 series gives the up to 48% better performance and up to 40% better performance in a virtualized...
Provided by Intel
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White Papers
High Speed Network Traffic Analysis With Commodity Multi-Core Systems
Jan 2010
Multi-core systems are the current dominant trend in computer processors. However, kernel network layers often do not fully exploit multi-core architectures. This is due to issues such as legacy...
Provided by Association for Computing Machinery
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White Papers
Towards Higher-Order Virtualization for Chip Multiprocessor Systems
Jan 2011
Parallelization and virtualization are rapidly becoming standard techniques on commodity platforms. The apparent trend is likely to continue in the foreseeable future. Indeed, there is significant...
Provided by University of Manchester
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White Papers
Virtualizing Hardware With Multi-Context Recon Gurable Arrays
Jan 2011
In contrast to processors, current reconfigurable devices totally lack programming models that would allow for device independent compilation and forward compatibility. The key to overcome this...
Provided by ETH Zurich
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White Papers
Hardware and Software Assists in Virtualization
Aug 2009
Until recently, embedded systems were often built with computing blocks containing a single CPU. Each block included a processor, memory controller and I/O bridge. This model has been a long-lived...
Provided by Freescale Semiconductor
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White Papers
Hiding Communication Latency With Non-SPMD, Graph-Based Execution
Feb 2009
Reformulating an algorithm to mask communication delays is crucial in maintaining scalability, but traditional solutions embed the overlap strategy into the application. The authors present an...
Provided by University of California
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White Papers
CYSEP - A Cyber-Security Processor for 10Gbps Networks and Beyond
Jan 2011
This paper describes the architecture of a CYber-SEcurity Processor (CYSEP) which can serve as a key module for enhancing security for high-speed networks/ systems. The CYSEP supports, at...
Provided by Lucent Technologies
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White Papers
Probabilistic Job Symbiosis Modeling for SMT Processor Scheduling
Mar 2010
Symbiotic job scheduling boosts Simultaneous Multithreading (SMT) processor performance by co-scheduling jobs that have 'Compatible' demands on the processor's shared resources. Existing...
Provided by Association for Computing Machinery
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White Papers
CAFE: A Framework for Cell Application Development
Dec 2007
The IBM Cell processor is a heterogeneous multi-core architecture designed to demonstrate exceptional levels of performance improvement for compute-intensive applications. The streamlined design...
Provided by University of California, San Diego
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White Papers
A Light-Weight Cache-Based Fault Detection and Checkpointing Scheme for MPSoCs Enabling Relaxed Execution Synchronization
Oct 2008
While technology advances have made MPSoCs a standard architecture for embedded systems, their applicability is increasingly being challenged by dramatic increases in the amount of device failures...
Provided by Association for Computing Machinery
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White Papers
Light-Weight Synchronization for Inter-Processor Communication Acceleration on Embedded MPSoCs
Oct 2007
Advances in semiconductor technologies have placed MPSoCs center stage as a standard architecture for embedded applications of ever increasing complexity. Efficient utilization of the ample...
Provided by Association for Computing Machinery
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White Papers
Predictable Execution Adaptivity Through Embedding Dynamic Reconfigurability Into Static MPSoC Schedules
Oct 2007
Advances in semiconductor technologies have placed MPSoCs center stage as a standard architecture for embedded applications of ever increasing complexity. Because of real-time constraints,...
Provided by Association for Computing Machinery
-
White Papers
Conservation Cores: Reducing the Energy of Mature Computations
Mar 2010
Growing transistor counts, limited power budgets, and the breakdown of voltage scaling are currently conspiring to create a utilization wall that limits the fraction of a chip that can run at full...
Provided by Association for Computing Machinery
-
White Papers
Scalability Aspects of Instruction Distribution Algorithms for Clustered Processors
Jan 2011
In the evolving sub-micron technology, importance of wire delays is growing, making it particularly attractive to use decentralized designs. A common form of decentralization adopted in processors...
Provided by Binghamton University
-
White Papers
Extending the Scalability of Single Chip Stream Processors With On-Chip Caches
Jun 2008
As semiconductor scaling continues, more transistors can be put onto the same chip despite growing challenges in clock frequency scaling. Stream processor architectures can make effective use of...
Provided by University of British Columbia
-
White Papers
Evaluating the Impact of Job Scheduling and Power Management on Processor Lifetime for Chip Multiprocessors
Jun 2009
Temperature-induced reliability issues are among the major challenges for multicore architectures. Thermal hot spots and thermal cycles combine to degrade reliability. This research presents new...
Provided by Association for Computing Machinery
-
White Papers
Accurate Branch Prediction for Short Threads
Mar 2008
Multi-core processors, with low communication costs and high availability of execution cores, will increase the use of execution and compilation models that use short threads to expose...
Provided by Association for Computing Machinery
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White Papers
Creating Artificial Global History to Improve Branch Prediction Accuracy
Jun 2009
Modern processors require highly accurate branch prediction for good performance. As such, a number of branch predictors have been proposed with varying size and complexity. This work identifies...
Provided by Association for Computing Machinery
-
White Papers
Reducing Peak Power With a Table-Driven Adaptive Processor Core
Dec 2009
The increasing power dissipation of current processors and processor cores constrains design options, increases packaging and cooling costs, increases power delivery costs, and decreases...
Provided by Association for Computing Machinery
-
White Papers
The Shared-Thread Multiprocessor
Jun 2008
This paper describes initial results for an architecture called the Shared-Thread Multiprocessor (STMP). The STMP combines features of a multithreaded processor and a chip multiprocessor;...
Provided by Association for Computing Machinery
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White Papers
Fast Thread Migration Via Cache Working Set Prediction
Dec 2010
The most significant source of lost performance when a thread migrates between cores is the loss of cache state. A significant boost in post-migration performance is possible if the cache working...
Provided by University of California, San Diego
-
White Papers
McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures
Dec 2009
This paper introduces McPAT, an integrated power, area, and timing modeling framework that supports comprehensive design space exploration for multicore and manycore processor configurations...
Provided by Association for Computing Machinery
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White Papers
Software Data Spreading: Leveraging Distributed Caches to Improve Single Thread Performance
Jun 2010
Single thread performance remains an important consideration even for multicore, multiprocessor systems. As a result, techniques for improving single thread performance using multiple cores have...
Provided by Association for Computing Machinery
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White Papers
Proving Optimizations Correct Using Parameterized Program Equivalence
Jun 2009
Translation validation is a technique for checking that, after an optimization has run, the input and output of the optimization are equivalent. Traditionally, translation validation has been used...
Provided by Association for Computing Machinery
-
White Papers
Say "Yes" to Dumb Operating Systems and Smart Applications
Jan 2008
The advent of Chip Multiprocessors (CMP) has spurred research on new OS scheduling algorithms that enable applications to make the most out of CMP systems. While many of these algorithms are very...
Provided by Simon Fraser University
-
White Papers
Dynamic Workload Characterization for Power Efficient Scheduling on CMP Systems
Aug 2010
Runtime characteristics of individual threads (Such as IPC, cache usage, etc.) are a critical factor in making efficient scheduling decisions in modern chip-multiprocessor systems. They provide...
Provided by Association for Computing Machinery
-
White Papers
Proximity-Aware Directory-Based Coherence for Multi-Core Processor Architectures
Jun 2007
As the number of cores increases on chip multiprocessors, coherence is fast becoming a central issue for multi-core performance. This is exacerbated by the fact that interconnection speeds are not...
Provided by Association for Computing Machinery
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White Papers
Design and Performance Evaluation of a New Irregular Fault-Tolerant Multistage Interconnection Network
Mar 2012
Inter-connecting processors and linking them efficiently to the memory modules in a parallel computer is not an easy task. Hence, an interconnection network that provides the desired connectivity...
Provided by International Journal of Computer Science Issues
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White Papers
Survey of NoC and Programming Models Proposals for MPSoC
Mar 2012
The aim of this paper is to give briefing of the concept of network-on-chip and programming model topics on multiprocessors System-on-Chip world, an attractive and relatively new field for...
Provided by International Journal of Computer Science Issues
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White Papers
Reconfigurable Co-Processor for High Performance Discrete Wavelet Transform
Jan 2012
Wavelet transforms have proven to be useful tool for several signal processing applications, including image and video compressions, image segmentation, speech synthesis and telecommunication....
Provided by Engg Journals Publications
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White Papers
Task Scheduling Algorithm to Reduce the Number of Processors Using Merge Conditions
Feb 2012
Some task scheduling algorithms generate the shortest schedule, when its input DAG satisfies a specified condition. Among those scheduling algorithms, TDS algorithm proposed a DAG condition where...
Provided by Engg Journals Publications
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White Papers
Performability Measures of Multiple Path Multistage Interconnection Networks
Feb 2012
In this paper, attempts have been made to develop different combinatorial models for evaluation performability of various multiple path Multistage Interconnection Networks (MINs). For the purpose...
Provided by Engg Journals Publications
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White Papers
A Parallel Access Method for Spatial Data Using GPU
Mar 2012
Spatial Access Methods (SAMs) are used for information retrieval in large spatial databases. Many of the SAMs use sequential tree structures to search the result set of the spatial data which are...
Provided by Engg Journals Publications
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White Papers
Performance Evaluation of a Simplified Matrix Processor
Feb 2012
Data parallel applications are growing in importance and demanding increased performance from hardware. Since, the fundamental data structures for a wide variety of data-parallel applications are...
Provided by The Second International Conference on Communications and Information Technology
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White Papers
Performance Evaluation of a 16.16 Fixed-Point Multiplier Implemented on the FALCON-A Processor
Feb 2012
This paper describes the implementation of a fixed point multiplier (using the 16.16 format) on the FALCON-A processor. Special assembly language coding techniques have been used to achieve the...
Provided by The Second International Conference on Communications and Information Technology
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White Papers
An Implementation of a MATLAB Compiler for Matrix Processors
Feb 2012
Not only did the compiler writers have to track new language features, they also had to devise translation algorithms that would take maximal advantage of the modern processors capabilities. This...
Provided by The Second International Conference on Communications and Information Technology
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White Papers
Issues in Caching Techniques to Improve System Performance in Chip Multiprocessors
Nov 2011
As cache management in chip multiprocessors has become more critical because of the diverse workloads, increasing working sets of many emerging applications, increasing memory latency and...
Provided by International Journal of Advances in Engineering & Technology (IJAET)
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White Papers
Design and Analysis of a Fault Tolerant Microprocessor Based on Triple Modular Redundancy Using VHDL
Mar 2011
There are numerous real time & operation critical systems in which the failure of the system is unacceptable at any stage of processing. The examples of such systems are like ATM machines,...
Provided by International Journal of Advances in Engineering & Technology (IJAET)
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White Papers
Design of Wireless Sensor Node and Time Contoured Control Scheme for a Composting Process
May 2011
This paper presents the design of wireless sensor node and a time contoured control scheme for a composting process. The electronic system is designed using Texas Instruments ultra low powered...
Provided by International Journal of Advances in Engineering & Technology (IJAET)
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White Papers
Design of Energy Aware Air Pollution Monitoring System Using WSN
May 2011
Wireless Sensor Network is a fast evolving technology having a number of potential applications in various domains of daily-life, such as structural and environmental monitoring, medicine,...
Provided by International Journal of Advances in Engineering & Technology (IJAET)
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White Papers
Implementation of User Interface for Microprocessor Trainer
Aug 2011
This paper aims to design and construct the microcontroller-based user interface system and to study input, computation, and output for microprocessor trainer. The other two activities beyond...
Provided by University of Computer Studies
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White Papers
A Vision for Next Generation Query Processors and an Associated Research Agenda
Jun 2009
Query processing is one of the most important mechanisms for data management, and there exist mature techniques for effective query optimization and efficient query execution. The vast majority of...
Provided by Aristotle University of Thessaloniki
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White Papers
Compact Implementation of Threefish and Skein on FPGA
Mar 2012
The SHA-3 finalist Skein is built from the tweakable Threefish block cipher. In order to have a better understanding of the computational efficiency of Skein (resource sharing, memory access...
Provided by Anadolu University
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Whitepapers
Itanium: Slip/Sliding Away...
Apr 2012
Oracle has followed the trend of other major ISVs and terminated further software development for the Itanium platform. Looking at the decline in revenue of HPs Itanium-based servers, combined...
Provided by IBM
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White Papers
Toward Practical Private Access to Data Centers Via Parallel ORAM
Mar 2012
Today, accessing maps, pictures, status updates, and other data from online services is de rigueur, but these accesses may leak private information. Previous work proposed using a secure...
Provided by Columbia University
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White Papers
Usable Assembly Language for GPUs: A Success Story
Mar 2012
The NVIDIA compilers nvcc and ptxas leave the programmer with only very limited control over register allocation, register spills, instruction selection, and instruction scheduling. In theory a...
Provided by University of Illinois
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White Papers
Design of Cache Controller for Multi-Core Processor System
Apr 2012
To meet the growing needs of computing power, communication speed and performance requirements demanded by today's applications, processor clock speed has to be increased. However, increasing...
Provided by G.H. Raisoni College of Engineering
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White Papers
Collision for 75-Step SHA-1: Intensive Parallelization With GPU
Nov 2011
The authors present a brief report on the collision search for the reduced SHA-1. With a few improvements to their previous work, directed at efficient parallelization on a GPU cluster, they...
Provided by International Association for Cryptologic Research
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White Papers
Security Enhancement of the Vortex Family of Hash Functions
May 2009
Vortex is a new family of one-way hash functions which has been submitted to the NIST SHA-3 competition. Its design is based on using the Rijndael block cipher round as a building block, and using...
Provided by Intel
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White Papers
SHA-3 on ARM11 Processors
Nov 2011
This paper presents high-speed assembly implementations of the 256-bit-output versions of all five SHA-3 finalists and of SHA-256 for the ARM11 family of processors. The authors report new speed...
Provided by National Taiwan University
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White Papers
Cryptanalysis of the Full AES Using GPU-Like Special-Purpose Hardware
Dec 2011
The block cipher Rijndael has undergone more than ten years of extensive cryptanalysis since its submission as a candidate for the Advanced Encryption Standard (AES) in April 1998. To date, most...
Provided by University of Luxembourg
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White Papers
Accelerating RSA Encryption Using Random Precalculations
Mar 2010
RSA encryption and digital signature algorithm is considered secure if keys are 1024 - 4096 bits long. Since, it requires modular exponentiation on numbers of this length, embedded systems need...
Provided by Budapest University of Technology and Economics
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White Papers
A New Parallel Window-Based Implementation of the Elliptic Curve Point Multiplication in Multi-Core Architectures
Mar 2012
Point multiplication is an important computation in elliptic curve cryptography. Various methods like binary method and window method have been implemented in the past for performing efficient...
Provided by National Institute of Technology, Durgapur
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White Papers
Accelerating Sparse Matrix Vector Multiplication on Many-Core GPUs
Jan 2012
Many-core GPUs provide high computing ability and substantial bandwidth; however, optimizing irregular applications like SpMV on GPUs becomes a difficult but meaningful task. In this paper, the...
Provided by Chinese Academy of Sciences
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White Papers
Using Shared Library Interposing for Transparent Application Acceleration in Systems With Heterogeneous Hardware Accelerators
Jul 2010
Today's computer systems increasingly comprise heterogeneous computing elements like multi-core processors, graphics processing units, and specialized co-processors, which allow parallel...
Provided by University of Paderborn
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White Papers
Direct N-Body Kernels for Multicore Platforms
Jun 2010
The authors present an inter-architectural comparison of single- and double-precision direct n-body implementations on modern multi-core platforms, including those based on the Intel Nehalem and...
Provided by Georgia Institute of Technology
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White Papers
Model-Driven Autotuning of Sparse Matrix-Vector Multiply on GPUs
Jan 2010
The authors present a performance model-driven framework for automated performance tuning (auto-tuning) of Sparse Matrix-Vector multiply (SpMV) on systems accelerated by Graphics Processing Units...
Provided by Association for Computing Machinery
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White Papers
On the Limits of GPU Acceleration
May 2010
This paper throws a small "Wet blanket" on the hot topic of GPGPU acceleration, based on experience analyzing and tuning both multithreaded CPU and GPU implementations of three computations in...
Provided by Georgia Institute of Technology
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White Papers
Leveraging Dominators for Preprocessing QBF
Dec 2009
Many CAD for VLSI problems can be naturally encoded as Quantified Boolean Formulas (QBFs) and solved with QBF solvers. Furthermore, such problems often contain circuit-based information that is...
Provided by University of Toronto
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White Papers
Simulation and Analysis of Audio Signal Processor
Oct 2011
An Audio Signal Processor analyze sound signals, process them and explore the signal properties. This paper is a part of the work carried out by the authors for designing the Audio Processor in...
Provided by International Journal of Computer Applications
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White Papers
A Comparative Analysis of Election Algorithm in Distributed Systems
Oct 2011
In distributed system, an important challenge faced is the adoption of efficient algorithms for coordinator election. The main role of an elected coordinator is to manage the use of a shared...
Provided by International Journal of Computer Applications
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White Papers
Optimum Body Biasing Technique in Domino Logic Gate Design for Low Power Applications
Dec 2011
Domino CMOS logic circuit family finds a wide variety of applications in microprocessors, digital signal processors, and dynamic memory due to their high speed and low device count. These dynamic...
Provided by International Journal of Computer Applications
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White Papers
Reconfigurable Network on Chip Router for Image Processing Based Multiprocessor Applications
Dec 2011
Real time Image Processing (I.P) systems, involving on board multiprocessor communication, use standard bus based communication. The load on the system to deliver the output towards real time...
Provided by International Journal of Computer Applications
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White Papers
A High-Throughput ASIC implementation of Configurable Advanced Encryption Standard (AES) Processor
Jan 2012
In this paper, a compact and fully pipelined ASIC implementation of AES cryptography algorithm has been presented. The proposed implementation is configurable to take 128, 192 and 256-bit keys...
Provided by International Journal of Computer Applications
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White Papers
Computing Worst Case Execution Time by Symbolically Executing a Time-Accurate Hardware Model
Jun 2011
To ensure that a program will respect all its timing constraints the authors must be able to compute a safe estimation of its Worst Case Execution Time (WCET). However, with the increasing...
Provided by ENSTA-École Nationale Supérieure de Techniques Avancées
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White Papers
Model-Based Programming of Intelligent Embedded Systems Through Offline Compilation
Sep 2011
Many recent and future space missions point to the need for increased autonomy in spacecraft with an emphasis on more capable fault diagnostic systems. The most widely used fault diagnostic...
Provided by International Journal of Engineering Trends and Technology
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White Papers
FPGA-Based, Multi-Processor HW-SW System for Single-Chip Crypto Applications
Oct 2010
This paper discusses design and analysis of an FPGA-based system containing two isolated, Altera Nios II softcore processors that share data through two custom cryptoengines. FPGA-based...
Provided by Rochester Institute of Technology
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White Papers
CYSEP - A Cyber-Security Processor for 10Gbps Networks and Beyond
Jan 2011
This paper describes the architecture of a CYber-SEcurity Processor (CYSEP) which can serve as a key module for enhancing security for high-speed networks/ systems. The CYSEP supports, at...
Provided by Lucent Technologies
-
White Papers
Probabilistic Job Symbiosis Modeling for SMT Processor Scheduling
Mar 2010
Symbiotic job scheduling boosts Simultaneous Multithreading (SMT) processor performance by co-scheduling jobs that have 'Compatible' demands on the processor's shared resources. Existing...
Provided by Association for Computing Machinery
-
White Papers
CAFE: A Framework for Cell Application Development
Dec 2007
The IBM Cell processor is a heterogeneous multi-core architecture designed to demonstrate exceptional levels of performance improvement for compute-intensive applications. The streamlined design...
Provided by University of California, San Diego
-
White Papers
A Light-Weight Cache-Based Fault Detection and Checkpointing Scheme for MPSoCs Enabling Relaxed Execution Synchronization
Oct 2008
While technology advances have made MPSoCs a standard architecture for embedded systems, their applicability is increasingly being challenged by dramatic increases in the amount of device failures...
Provided by Association for Computing Machinery
-
White Papers
Light-Weight Synchronization for Inter-Processor Communication Acceleration on Embedded MPSoCs
Oct 2007
Advances in semiconductor technologies have placed MPSoCs center stage as a standard architecture for embedded applications of ever increasing complexity. Efficient utilization of the ample...
Provided by Association for Computing Machinery
-
White Papers
Predictable Execution Adaptivity Through Embedding Dynamic Reconfigurability Into Static MPSoC Schedules
Oct 2007
Advances in semiconductor technologies have placed MPSoCs center stage as a standard architecture for embedded applications of ever increasing complexity. Because of real-time constraints,...
Provided by Association for Computing Machinery
-
White Papers
Conservation Cores: Reducing the Energy of Mature Computations
Mar 2010
Growing transistor counts, limited power budgets, and the breakdown of voltage scaling are currently conspiring to create a utilization wall that limits the fraction of a chip that can run at full...
Provided by Association for Computing Machinery
-
White Papers
Scalability Aspects of Instruction Distribution Algorithms for Clustered Processors
Jan 2011
In the evolving sub-micron technology, importance of wire delays is growing, making it particularly attractive to use decentralized designs. A common form of decentralization adopted in processors...
Provided by Binghamton University
-
White Papers
Extending the Scalability of Single Chip Stream Processors With On-Chip Caches
Jun 2008
As semiconductor scaling continues, more transistors can be put onto the same chip despite growing challenges in clock frequency scaling. Stream processor architectures can make effective use of...
Provided by University of British Columbia
-
White Papers
Evaluating the Impact of Job Scheduling and Power Management on Processor Lifetime for Chip Multiprocessors
Jun 2009
Temperature-induced reliability issues are among the major challenges for multicore architectures. Thermal hot spots and thermal cycles combine to degrade reliability. This research presents new...
Provided by Association for Computing Machinery
-
White Papers
Accurate Branch Prediction for Short Threads
Mar 2008
Multi-core processors, with low communication costs and high availability of execution cores, will increase the use of execution and compilation models that use short threads to expose...
Provided by Association for Computing Machinery
-
White Papers
Creating Artificial Global History to Improve Branch Prediction Accuracy
Jun 2009
Modern processors require highly accurate branch prediction for good performance. As such, a number of branch predictors have been proposed with varying size and complexity. This work identifies...
Provided by Association for Computing Machinery
-
White Papers
Reducing Peak Power With a Table-Driven Adaptive Processor Core
Dec 2009
The increasing power dissipation of current processors and processor cores constrains design options, increases packaging and cooling costs, increases power delivery costs, and decreases...
Provided by Association for Computing Machinery
-
White Papers
The Shared-Thread Multiprocessor
Jun 2008
This paper describes initial results for an architecture called the Shared-Thread Multiprocessor (STMP). The STMP combines features of a multithreaded processor and a chip multiprocessor;...
Provided by Association for Computing Machinery
-
White Papers
Fast Thread Migration Via Cache Working Set Prediction
Dec 2010
The most significant source of lost performance when a thread migrates between cores is the loss of cache state. A significant boost in post-migration performance is possible if the cache working...
Provided by University of California, San Diego
-
White Papers
McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures
Dec 2009
This paper introduces McPAT, an integrated power, area, and timing modeling framework that supports comprehensive design space exploration for multicore and manycore processor configurations...
Provided by Association for Computing Machinery
-
White Papers
Software Data Spreading: Leveraging Distributed Caches to Improve Single Thread Performance
Jun 2010
Single thread performance remains an important consideration even for multicore, multiprocessor systems. As a result, techniques for improving single thread performance using multiple cores have...
Provided by Association for Computing Machinery
-
White Papers
Proving Optimizations Correct Using Parameterized Program Equivalence
Jun 2009
Translation validation is a technique for checking that, after an optimization has run, the input and output of the optimization are equivalent. Traditionally, translation validation has been used...
Provided by Association for Computing Machinery
-
White Papers
Say "Yes" to Dumb Operating Systems and Smart Applications
Jan 2008
The advent of Chip Multiprocessors (CMP) has spurred research on new OS scheduling algorithms that enable applications to make the most out of CMP systems. While many of these algorithms are very...
Provided by Simon Fraser University
-
White Papers
Dynamic Workload Characterization for Power Efficient Scheduling on CMP Systems
Aug 2010
Runtime characteristics of individual threads (Such as IPC, cache usage, etc.) are a critical factor in making efficient scheduling decisions in modern chip-multiprocessor systems. They provide...
Provided by Association for Computing Machinery
-
White Papers
Proximity-Aware Directory-Based Coherence for Multi-Core Processor Architectures
Jun 2007
As the number of cores increases on chip multiprocessors, coherence is fast becoming a central issue for multi-core performance. This is exacerbated by the fact that interconnection speeds are not...
Provided by Association for Computing Machinery
-
White Papers
Low-Power Branch Target Buffer for Application-Specific Embedded Processors
Jan 2011
In this paper the authors present a methodology for a low-power branch identification mechanism, which enables the design of extremely power efficient branch predictors for embedded processors....
Provided by University of California, San Diego
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White Papers
Dynamic Processors Demand Dynamic Operating Systems
Jun 2010
The rise of multicore processors has lead to techniques that dynamically vary the set and characteristics of cores or threads available to the operating system. For example, Core Fusion merges...
Provided by University of Wisconsin
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White Papers
Adapting to Intermittent Faults in Future Multicore Systems
Jul 2007
As technology continues to scale, future multicore processors become more susceptible to a variety of hardware failures. In particular, intermittent faults are expected to become especially...
Provided by University of Wisconsin
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White Papers
WrtVMM: A Virtual Machine Monitor for Embedded Devices
Dec 2009
The authors built a virtual machine monitor for the Linksys WRT54GL wireless router to run Embedded Xinu as a guest OS within OpenWrt. The system uses a kernel module and signal handlers to...
Provided by University of Wisconsin
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White Papers
Disco: Running Commodity Operating Systems on Scalable Multiprocessors
Jan 2011
In this paper the authors examine the problem of extending modern operating systems to run efficiently on large-scale shared memory multiprocessors without a large implementation effort. The...
Provided by Stanford University
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White Papers
PROPHET: Goal-Oriented Provisioning for Highly Tunable Multicore Processors in Cloud Computing
Jan 2011
As multicore and future many-core processors emerge with more complex optimization features, how to achieve optimal efficiency in terms of energy, power, and performance when running parallel...
Provided by Georgia Institute of Technology
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White Papers
Power-Efficient DRAM Speculation
Dec 2007
Power-Efficient DRAM Speculation (PEDS) is a power optimization targeted at broadcast-based shared memory multiprocessor systems that speculatively access DRAM in parallel with the broadcast...
Provided by University of Wisconsin
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White Papers
Combining Processor Virtualization and Split Compilation for Heterogeneous Multicore Embedded Systems
Feb 2009
Complex embedded systems have always been heterogeneous multicore systems. Because of the tight constraints on power, performance and cost, this situation is not likely to change any time soon. As...
Provided by INRIA
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White Papers
Achieving Technical and Business Benefits Through Processor Virtualization: Everybody Into the Pool!
Dec 2009
The University of Pittsburgh Medical Center (UPMC), an $8 billion global health enterprise, utilizes IBM Power Systems servers and AIX to operate many of its business critical databases and...
Provided by University of Pittsburgh
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White Papers
Isolation in Commodity Multicore Processors
Jun 2007
Technology scaling and power trends have led to the widespread emergence of Chip Multiprocessors (CMPs) as the predominant hardware paradigm. 1 Multiple cores are being integrated on a single chip...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Multiprocessor Scheduling Using Dynamic Performance Measurement and Analysis
Jan 2011
In this paper the authors address using dynamic performance metrics when making scheduling decisions. The focus is on the problem of cache affinity in multiprocessor CPU schedulers. The Linux 2.4...
Provided by University of Wisconsin
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White Papers
Optimizing a Multi-Core Processor for Message-Passing Workloads
Apr 2009
Future large-scale multi-cores will likely be best suited for use within High-Performance Computing (HPC) domains. A large fraction of HPC workloads employ the Message Passing Interface (MPI), yet...
Provided by University of Utah
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White Papers
EXACT: Explicit Dynamic-Branch Prediction With Active Updates
May 2010
Branches that depend directly or indirectly on load instructions are a leading cause of mispredictions by state-of-the-art branch predictors. For a branch of this type, there is a unique dynamic...
Provided by Association for Computing Machinery
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White Papers
A 65 nm 2-Billion Transistor Quad-Core Itanium Processor
Jan 2009
This paper describes an Itanium processor implemented in 65 nm process with 8 layers of Cu interconnect. The 21.5 mm by 32.5 mm die has 2.05B transistors. The processor has four dual-threaded...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Characterization of Embedded Applications for Decoupled Processor Architecture
Jan 2011
Needs for performance on embedded applications will lead to the use of dynamic execution on embedded processors in the next few years. However, complete out-of-order superscalar cores are still...
Provided by IRISA
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Whitepapers
Load Balancing in Grid Computing
May 2011
Computing grids are conceptually not unlike electrical grids. Grid computing uses middleware to coordinate disparate IT resources across a network, allowing them to function as a virtual whole....
Provided by International forum of researchers Students and Academician
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White Papers
Power-Efficient Instruction Encoding Optimization for Various Architecture Classes
Mar 2008
A huge application domain, in particular, wireless and handheld devices strongly requires flexible and powerefficient hardware with high performance. This can only be achieved with Application...
Provided by Academy Publisher
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White Papers
Design of a Numerical Adaptive Relay Based on Memory Mapped Techniques
Mar 2009
This work describes the design of a DSP (Digital Signal Processor) based Adaptive Numerical Mho relay, to be used for distance protection schemes of long distance transmission lines. The relay...
Provided by International Association of Engineers
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White Papers
Intelligent Co-Operative Pim Architecture for Image Analysis and Pattern Recognition
Mar 2010
Computer memory systems are increasingly a bottleneck limiting application performance. Processor-In-Memory (PIM) architectures, which capitalize on merging the processing unit with its memory...
Provided by Aalborg University
