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Mission Statement
TechRepublic's ITPapers is the Web's largest library of free technical IT white papers, webcasts, and case studies. Covering IT categories including Data Management, IT Management, Networking, Communications, Enterprise Applications, Storage, Security and much more, TechRepublic's White Paper Directory is the best source for technical white papers and IT information.
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White Papers
A Holistic Approach for Performance Measurement and Analysis for Petascale Applications
Mar 2009
Contemporary high-end Terascale and Petascale systems are composed of hundreds of thousands of commodity multi-core processors interconnected with high-speed custom networks. Performance...
Provided by University of Oregon
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White Papers
Grouping-Based Dynamic Power Management for Multi-Threaded Programs in Chip-Multiprocessors
May 2009
In the embedded systems field, the research focus has shifted from performance to considering both performance and power consumption. Previous research has investigated methods to forecast the...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Parallel Database Sort and Join Operations Revisited on Grids
Sep 2007
Based on the renowned method of Bitton et al. (see) the authors develop a concise but comprehensive analytical model for the well-known Binary Merge Sort, Bitonic Sort, Nested-Loop Join and Sort...
Provided by Springer Science+Business Media
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White Papers
Concurrent Number Cruncher: An Efficient Sparse Linear Solver on the GPU
Sep 2007
A wide class of geometry processing and PDE resolution methods needs to solve a linear system, where the non-zero pattern of the matrix is dictated by the connectivity matrix of the mesh. The...
Provided by Springer Science+Business Media
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White Papers
Parallel Multistage Preconditioners Based on a Hierarchical Graph Decomposition for SMP Cluster Architectures With a Hybrid Parallel Programming Model
Sep 2007
In this work, the Parallel Hierarchical Interface Decomposition Algorithm (PHIDAL) and a hybrid parallel programming model were applied to finite-element based simulations of linear elasticity...
Provided by Springer Science+Business Media
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White Papers
Strategies and Implementation for Translating OpenMP Code for Clusters
Sep 2007
OpenMP is a portable shared memory programming interface that promises high programmer productivity for multithreaded applications. It is designed for small and middle sized shared memory systems....
Provided by Springer Science+Business Media
-
White Papers
FROCM: A Fair and Low-Overhead Method in SMT Processor
Sep 2007
Simultaneous Multithreading (SMT) and Chip Multiprocessors (CMP) processors have emerged as the mainstream computing platform in major market segments, including PC, server, and embedded domains....
Provided by Springer Science+Business Media
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White Papers
An Exploration of Performance Attributes for Symbolic Modeling of Emerging Processing Devices
Sep 2007
Vector, emerging (homogenous and heterogeneous) multi-core and a number of accelerator processing devices potentially offer an order of magnitude speedup for scientific applications that are...
Provided by Springer Science+Business Media
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White Papers
Towards Scalable Event Tracing for High End Systems
Sep 2007
Although event tracing of parallel applications offers highly detailed performance information, tracing on current leading edge systems may lead to unacceptable perturbation of the target program...
Provided by Springer Science+Business Media
-
White Papers
Energy Efficient Packet Classification Hardware Accelerator
Mar 2008
Packet classification is an important function in a router's line-card. Although many excellent solutions have been proposed in the past, implementing high speed packet classification reaching up...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
System-Level, Thermal-Aware, Fully-Loaded Process Scheduling
Mar 2008
Processor power consumption produces significant heat and can result in higher average operating temperatures. High operating temperatures can lead to reduced reliability and at times thermal...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
What to Make of Multicore Processors for Reliable Real-Time Systems?
Apr 2010
Now that multicore microprocessors have become a commodity, it is natural to think about employing them in all kinds of computing, including high-reliability embedded real-time systems. Appealing...
Provided by Florida State University
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White Papers
Brute-Force Determination of Multiprocessor Schedulability for Sets of Sporadic Hard-Deadline Tasks
Jun 2007
This paper describes a necessary and sufficient test for the schedulability of a set of sporadic hard-deadline tasks on a multiprocessor platform, using any of a variety of scheduling policies...
Provided by Florida State University
-
White Papers
QP: A Heterogeneous Multi-Accelerator Cluster
Mar 2009
The authors present a heterogeneous multi-accelerator cluster developed and deployed at NCSA. The cluster consists of 16 AMD dual-core CPU compute nodes each with four NVIDIA GPUs and one Xilinx...
Provided by University of Illinois
-
White Papers
Evaluation of Two-Electron Repulsion Integrals Over Gaussian Basis Functions on SRC-6 Reconfigurable Computer
Oct 2008
The authors demonstrate an implementation of the two-electron repulsion integrals code for the direct self-consistent field calculations on a reconfigurable computer. They analyze different...
Provided by University of Illinois
-
White Papers
NBTI-Aware Dynamic Instruction Scheduling
Mar 2009
NBTI is an important emerging silicon reliability problem. In this paper the authors explore a microarchitecture-level approach to mitigate NBTI related failures in the functional units of a...
Provided by University of Virginia
-
White Papers
Modeling and Analyzing NBTI in the Presence of Process Variation
Dec 2010
With continuous scaling of transistors in each technology generation, NBTI and Process Variation (PV) have become very important silicon reliability problems for the microprocessor industry. In...
Provided by University of Virginia
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White Papers
A Benchmark Suite for Unstructured Data Processing
Nov 2007
A large fraction of the data that will stored and accessed in future systems is expected to be unstructured, in the form of images, audio files, etc. Therefore, it is very important to design...
Provided by University of Virginia
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White Papers
Medium-Grain Cells for Reconfigurable DSP Hardware
Jun 2007
Reconfigurable hardware contains an array of programmable cells and interconnection structures. Field-programmable gate arrays use fine-grain cells that implement simple logic functions. Some...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Reducing Power in Memory Decoders by Means of Selective Precharge Schemes
May 2007
Two novel memory decoder designs for reducing energy consumption and delay are presented in this paper. These two decoding schemes are compared to the conventional NOR decoder. Fewer word lines...
Provided by Washington State University
-
White Papers
Representative Multiprogram Workloads for Multithreaded Processor Simulation
Jan 2011
Almost all new consumer-grade processors are capable of executing multiple programs simultaneously. The analysis of multiprogrammed workloads for multicore and SMT processors is challenging and...
Provided by University of California
-
White Papers
Criticality-Based Optimizations for Efficient Load Processing
Feb 2009
Some instructions have more impact on processor performance than others. Identification of these critical instructions can be used to modify and improve instruction processing. Previous work has...
Provided by Georgia Institute of Technology
-
White Papers
Thermal Optimization in Multi-Granularity Multi-Core Floorplanning
Jan 2009
Multi-core microarchitectures require a careful balance between many competing objectives to achieve the highest possible performance. Integrated Early Analysis is the consideration of all of...
Provided by Georgia Institute of Technology
-
White Papers
The Cost of Uncore in Throughput-Oriented Many-Core Processors
Jun 2008
Achieving performance through traditional techniques such as extracting more instruction level parallelism or increasing clock frequencies are losing their effectiveness due to the power wall....
Provided by Georgia Institute of Technology
-
White Papers
Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors
Mar 2008
3D integration technology greatly increases transistor density while providing faster on-chip communication. 3D implementations of processors can simultaneously provide both latency and power...
Provided by Georgia Institute of Technology
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White Papers
Cache Vulnerability Equations for Protecting Data in Embedded Processor Caches From Soft Errors
Apr 2010
Continuous technology scaling has brought one to a point, where transistors have become extremely susceptible to cosmic radiation strikes, or soft errors. Inside the processor, caches are most...
Provided by Association for Computing Machinery
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White Papers
Code Transformations for TLB Power Reduction
Dec 2009
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB though small is...
Provided by Springer Science+Business Media
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White Papers
A Software Solution for Dynamic Stack Management on Scratch Pad Memory
Nov 2008
In an effort to make processors more power efficient Scratch Pad Memory (SPM) have been proposed instead of caches, which can consume majority of processor power. However, application mapping on...
Provided by Arizona State University
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White Papers
Hiding Cache Miss Penalty Using Priority-Based Execution for Embedded Processors
Nov 2007
The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-end processors can...
Provided by Seoul National University
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White Papers
NWSLite: A General-Purpose, 32 Nonparametric Prediction Utility for Embedded Systems
Apr 2008
Time series-based prediction methods have a wide range of uses in embedded systems. Many OS algorithms and applications require accurate prediction of demand and supply of resources. However,...
Provided by Association for Computing Machinery
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White Papers
Dynamically Managed Multithreaded Reconfigurable Architectures for Chip Multiprocessors
Sep 2010
Prior work has demonstrated that reconfigurable logic can significantly benefit certain applications. However, reconfigurable architectures have traditionally suffered from high area overhead and...
Provided by Association for Computing Machinery
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White Papers
Enabling Parallelization Via a Reconfigurable Chip Multiprocessor
May 2010
While reconfigurable computing has traditionally involved attaching a reconfigurable fabric to a single processor core, the prospect of large-scale CMPs calls for a reevaluation of reconfigurable...
Provided by Cornell University
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White Papers
Dynamic Software Updates for Real-Time Systems
Oct 2009
Seamlessly updating software in running systems has recently gained momentum. Dynamically updating the software of real-time embedded systems, however, still poses numerous challenges: such...
Provided by Association for Computing Machinery
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White Papers
An Online Optimization-Based Technique for Dynamic Resource Allocation in GPS Servers
Jan 2011
Since web workloads are known to vary dynamically with time, in this paper, the authors argue that dynamic resource allocation techniques are necessary in the presence of such workloads to provide...
Provided by University of Massachusetts
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White Papers
Pre-Analyzed Resource and Time Provisioning in Distributed Real-Time Systems: An Application to Mobile Robotics
Jan 2011
The work is motivated by mobile robotic applications where a team of autonomous robots cooperate in achieving a goal, e.g., using sensor feeds to locate trapped humans in a building on fire. To...
Provided by University of Massachusetts
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White Papers
Quanto: Tracking Energy in Networked Embedded Systems
Oct 2008
This paper presents Quanto, a network-wide time and energy profiler for embedded network devices. By combining well-defined interfaces for hardware power states, fast high-resolution energy...
Provided by Stanford University
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White Papers
Cross-Component Energy Management: Joint Adaptation of Processor and Memory
Sep 2007
Researchers have proposed the use of adaptation to reduce the energy consumption of different hardware components, such as the processor, memory, disk, and display for general-purpose...
Provided by Association for Computing Machinery
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White Papers
Statistical Fault Injection
Mar 2008
It is well known that soft errors in logic are a concern in modern VLSI circuits. Recent studies on the IBM POWER6 microprocessor using particle-beam irradiation and full core Statistical Fault...
Provided by University of Illinois at Urbana Champaign
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White Papers
MSWAT: Low-Cost Hardware Fault Detection and Diagnosis for Multicore Systems
Oct 2009
Continued technology scaling is resulting in systems with billions of devices. Unfortunately, these devices are prone to failures from various sources, resulting in even commodity systems being...
Provided by Association for Computing Machinery
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Whitepapers
A New Reduced Clock Power Flip-Flop for Future SOC Applications
Aug 2012
In this paper a novel technique is proposed based on the comparison between Conventional Conditional Data Mapping Flip-flop and Clock Pair Shared D Flip Flop (CPSFF) here the authors are checking...
Provided by IJCTT-International Journal of Computer Trends and Technology
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White Papers
Model-Based Programming of Intelligent Embedded Systems Through Offline Compilation
Sep 2011
Many recent and future space missions point to the need for increased autonomy in spacecraft with an emphasis on more capable fault diagnostic systems. The most widely used fault diagnostic...
Provided by International Journal of Engineering Trends and Technology
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White Papers
FPGA-Based, Multi-Processor HW-SW System for Single-Chip Crypto Applications
Oct 2010
This paper discusses design and analysis of an FPGA-based system containing two isolated, Altera Nios II softcore processors that share data through two custom cryptoengines. FPGA-based...
Provided by Rochester Institute of Technology
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Case Studies
ERCO&GENER: Turnkey M2M Data Collection With Universal Socket Connectivity Equals Off-the Shelf Solutions
Jan 2008
ERCO & GENER has been providing the M2M market with turnkey and off-the-shelf solutions. Their challenge is that applications such as remote surveillance and remote maintenance requiring...
Provided by Multi-Tech Systems
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White Papers
Configurable M-Factor VLSI DVB-S2 LDPC Decoder Architecture With Optimized Memory Tiling Design
Mar 2012
Semi-parallel architectures for decoding Digital Video Broadcasting-Satellite 2 (DVB-S2) Low-Density Parity-Check (LDPC) codes have improved Very Large Scale Integration (VLSI) solutions, but...
Provided by EURASIP
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White Papers
Performance Evaluation of Dynamic Speculative Multithreading With the Cascadia Architecture
Jan 2012
Thread-Level Parallelism (TLP) has been extensively studied in order to overcome the limitations of exploiting Instruction-Level Parallelism (ILP) on high-performance superscalar processors. One...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Transaction-Based Communication-Centric Debug
Jan 2012
The behaviour of Systems On Chip (SOC) is complex because they contain multiple processors that interact through concurrent interconnects, such as Networks On Chip (NOC). Debugging such SOCs is...
Provided by University of Twente
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White Papers
Performance Analysis of Soft and Hard Single-Hop and Multi-Hop Circuit-Switched Interconnects for FPGAs
Jul 2008
This paper presents a performance analysis of hard and soft on-chip networks for FPGAs. The authors applied the Jackson's queuing model to analyze the performance of a MultiProcessor System on a...
Provided by Delft University of Technology
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White Papers
A Network-on-Chip Monitoring Infrastructure for Communication-Centric Debug of Embedded Multi-Processor SoCs
Mar 2009
Problems in a new System On Chip (SOC) consisting of hardware and embedded software often only show up when a silicon prototype of the chip is placed in its intended target environment and the...
Provided by Delft University of Technology
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White Papers
Conservative Dynamic Energy Management for Real-Time Dataflow Applications Mapped on Multiple Processors
Jun 2009
Voltage-Frequency Scaling (VFS) trades a linear processor slowdown for a potentially quadratic reduction in energy consumption. Complex dependencies may exist between different tasks of an...
Provided by Delft University of Technology
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White Papers
A Distributed Architecture to Check Global Properties for Post-Silicon Debug
Mar 2010
Post-silicon validation and debug, or ensuring that software executes correctly on the silicon of a Multi-Processor System-On-Chip (MPSOC) is complicated, as it involves checking global properties...
Provided by Eindhoven University of Technology (TU/e)
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White Papers
A Composable, Energy-Managed, Real-Time MPSOC Platform
Apr 2010
Multi-Processors Systems On Chip (MPSOC) platforms emerged in embedded systems as hardware solutions to support the continuously increasing functionality and performance demands in this domain....
Provided by Delft University of Technology
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White Papers
Conservative Application-Level Performance Analysis Through Simulation of MPSoCs
Dec 2010
Applications, often with real-time requirements, are mapped onto Multi-Processor Systems on Chip (MPSoCs). Hard real-time applications require no deadline misses, and a formal modelling approach...
Provided by Technische Universitat Darmstadt
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White Papers
Design and Implementation of an Operating System for Composable Processor Sharing
Sep 2010
Multi-Processor Systems on Chip (MPSoC) run multiple independent applications, often developed by different parties. The applications share the hardware resources, e.g. processors, memories and...
Provided by Reed Elsevier
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White Papers
Resource-Efficient Real-Time Scheduling Using Credit-Controlled Static-Priority Arbitration
Jun 2011
A present-day System-on-Chip (SoC) runs a wide range of applications with diverse real-time requirements. Resources, such as processors, interconnects and memories, are shared between these...
Provided by Eindhoven University of Technology (TU/e)
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White Papers
Process-Variation Aware Mapping of Real-Time Streaming Applications to MPSoCs for Improved Yield
Dec 2011
As technology scales, the impact of process variation on the MAXimum supported Frequency (FMAX) of individual cores in a MPSoC becomes more pronounced. Task allocation without variation-aware...
Provided by Delft University of Technology
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White Papers
Hierarchical Segmentation for Hardware Function Evaluation
Dec 2008
This paper presents a method for evaluating functions based on piecewise polynomial approximations (splines) with a hierarchical segmentation scheme targeting hardware implementation. The...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
A Heterogeneous Multicore System on Chip With Run-Time Reconfigurable Virtual FPGA Architecture
Dec 2010
System design, especially for low power embedded applications often profit from a heterogeneous target hardware platform. The application can be partitioned into modules with specific...
Provided by National Technical University of Athens
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White Papers
Quick Hotspot: A Software Supported Methodology for Supporting Run-Time Thermal Analysis at MPSoC Designs
Jan 2011
Detailed thermal analysis and exploration has recently received significant attention since it is straightforward-related to numerous reliability issues. Furthermore, thermal profiling is a...
Provided by National Technical University of Athens
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White Papers
Thermal Optimization for Micro-Architectures Through Selective Block Replication
May 2011
Increased power densities result to higher on-chip temperatures, which in turn creates numerous problems tightly firmed to reliability issues. This problem is expected to become even more severe...
Provided by National Technical University of Athens
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White Papers
Trading Fault-Masking With Performance Overhead for FPGAs
Jan 2011
Reliability issues become an important design concern with technology scaling. This paper introduces a novel methodology for balancing the desired fault masking and the consequence delay and power...
Provided by National Technical University of Athens
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White Papers
A Framework for Enabling Fault Tolerance in Reconfigurable Architectures
Dec 2009
Fault tolerance is a pre-request not only for safety critical systems, but almost for the majority of applications. However, the additional hardware elements impose performance degradation. In...
Provided by National Technical University of Athens
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White Papers
Towards Supporting Fault-Tolerance in FPGAs
Apr 2010
This paper proposes a novel methodology for improving reliability of FPGAs without requiring special purpose hardware. In contrast to related approaches that are applied uniformly over the target...
Provided by National Technical University of Athens
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White Papers
Fault-Free: A Framework for Supporting Fault Tolerance in FPGAs
Nov 2009
In this paper, the authors propose a novel methodology for supporting application mapping onto FPGAs with fault tolerance even if this feature is not supported by the target platform. For the...
Provided by National Technical University of Athens
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White Papers
Three Dimensional FPGA Architectures: A Shift Paradigm for Energy-Performance Efficient DSP Implementations
Jan 2012
Modern applications exhibit increased complexity which introduces extra constraints during implementation related to delay, power consumption and silicon area. This problem is even more important...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
A Novel Methodology for Exploring Interconnection Architectures Targeting 3-D FPGAs
Dec 2008
In current reconfigurable architectures the interconnection structures increasingly contribute more to the delay and power consumption. The demand for increased clock frequencies and logic density...
Provided by National Technical University of Athens
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White Papers
System-Level Exploration of 3-D Interconnection Schemes
Nov 2008
3-D chip stacking is the big next step in system integration. Even though the process technology is maturing, many issues related to system implementation are not fully understood yet....
Provided by National Technical University of Athens
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White Papers
A Software-Supported Methodology for Exploring Interconnection Architectures Targeting 3-D FPGAs
Jan 2009
Interconnect structures significantly contribute to the delay, power consumption, and silicon area of modern reconfigurable architectures. The demand for higher clock frequencies and logic...
Provided by National Technical University of Athens
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White Papers
A Novel Methodology for Architecture-Level Exploration of 3D SoCs
May 2011
Three-Dimensional (3D) integration is an emerging technology that is expected to lead to tremendous benefits in terms of power, delay and silicon area. Moreover, 3D technology continues...
Provided by National Technical University of Athens
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White Papers
Defending Embedded Systems Against Control Flow Attacks
Nov 2009
This paper presents a control flow enforcement technique based on an Instruction Based Memory Access Control (IBMAC) implemented in hardware. It is specifically designed to protect low-cost...
Provided by Association for Computing Machinery
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White Papers
An Improved MIP-Based Policy for Deadlock Prevention Based on Petri Nets
Sep 2011
Deadlocks are undesired in highly automated flexible manufacturing systems. The Mixed Integer Programming (MIP)-based deadlock prevention method is considered as one of the most efficient methods...
Provided by Zhejiang Gongshang University
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White Papers
A Scheduling With DVS Mechanism for Embedded Multi-Core Real-Time Systems
Apr 2011
With the advancement of technology, embedded systems have been widely used in portable devices. Portable embedded systems must have rather superior computing capability in order to meet real-time...
Provided by Tatung University
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White Papers
Using Game Theory for Scheduling Tasks on Multi-Core Processors for Simultaneous Optimization of Performance and Energy
Jan 2009
Multi-core processors are beginning to revolutionize the landscape of high-performance computing. In this paper, the authors address the problem of power-aware scheduling/mapping of tasks onto...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Memory System Performance in a NUMA Multicore Multiprocessor
Jun 2011
Modern multi-core processors with an on-chip memory controller form the base for NUMA (non-uniform memory architecture) multiprocessors. Each processor accesses part of the physical memory...
Provided by Association for Computing Machinery
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White Papers
Power Efficient Rate Monotonic Scheduling for Multi-Core Systems
Jul 2011
More computational power is offered by current real-time systems to cope with CPU intensive applications. However, this facility comes at the price of more energy consumption and eventually higher...
Provided by Reed Elsevier
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White Papers
Genetic Algorithm for Multiprocessor Task Scheduling
Aug 2011
MultiProcessor Task Scheduling (MPTS) is an important and computationally difficult problem. Multiprocessors have emerged as a powerful computing means for running real-time applications...
Provided by International Journal of Computer Science and Management Studies
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White Papers
Unavoidability Routine Enrichment for Real-Time Embedded Systems by Using Cache-Locking Technique
Jan 2012
In multitask, preemptive real-time systems, the use of cache memories make difficult the estimation of the response time of tasks, due to the dynamic, adaptive and non predictable behavior of...
Provided by International Journal of Electronics Communication and Computer Engineering
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White Papers
Hardware Software Co-Design for Low Cost Embedded Systems Based on FPGA
Jan 2012
The fundamental building blocks of a SoC (System on Chip) are its Intellectual Property (IP) cores, which are reusable hardware blocks designed to perform a particular task. For realizing SoC...
Provided by International Journal of Electronics Communication and Computer Engineering
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White Papers
Robust Digital Image Watermarking Using Region Adaptive Embedding Technique
Jun 2011
Improving the robustness of watermark in withstanding attacks has been one of the main research objectives in digital image watermarking. In this paper, the authors propose a novel region-adaptive...
Provided by Liverpool John Moores University
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White Papers
CPM in CMPs: Coordinated Power Management in Chip-Multiprocessors
Nov 2010
Multiple clock domain architectures have recently been proposed to alleviate the power problem in CMPs by having different frequency/voltage values assigned to each domain based on workload...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Finding Deadlocks of Event-B Models by Constraint Solving
Jun 2011
Establishing the absence of deadlocks is important in many applications of formal methods. The use of model checking for finding deadlocks in formal models is limited because in many industrial...
Provided by Heinrich Heine Universitat Dusseldorf
-
White Papers
Parallel Database Sort and Join Operations Revisited on Grids
Sep 2007
Based on the renowned method of Bitton et al. (see) the authors develop a concise but comprehensive analytical model for the well-known Binary Merge Sort, Bitonic Sort, Nested-Loop Join and Sort...
Provided by Springer Science+Business Media
-
White Papers
Concurrent Number Cruncher: An Efficient Sparse Linear Solver on the GPU
Sep 2007
A wide class of geometry processing and PDE resolution methods needs to solve a linear system, where the non-zero pattern of the matrix is dictated by the connectivity matrix of the mesh. The...
Provided by Springer Science+Business Media
-
White Papers
Parallel Multistage Preconditioners Based on a Hierarchical Graph Decomposition for SMP Cluster Architectures With a Hybrid Parallel Programming Model
Sep 2007
In this work, the Parallel Hierarchical Interface Decomposition Algorithm (PHIDAL) and a hybrid parallel programming model were applied to finite-element based simulations of linear elasticity...
Provided by Springer Science+Business Media
-
White Papers
Strategies and Implementation for Translating OpenMP Code for Clusters
Sep 2007
OpenMP is a portable shared memory programming interface that promises high programmer productivity for multithreaded applications. It is designed for small and middle sized shared memory systems....
Provided by Springer Science+Business Media
-
White Papers
FROCM: A Fair and Low-Overhead Method in SMT Processor
Sep 2007
Simultaneous Multithreading (SMT) and Chip Multiprocessors (CMP) processors have emerged as the mainstream computing platform in major market segments, including PC, server, and embedded domains....
Provided by Springer Science+Business Media
-
White Papers
An Exploration of Performance Attributes for Symbolic Modeling of Emerging Processing Devices
Sep 2007
Vector, emerging (homogenous and heterogeneous) multi-core and a number of accelerator processing devices potentially offer an order of magnitude speedup for scientific applications that are...
Provided by Springer Science+Business Media
-
White Papers
Towards Scalable Event Tracing for High End Systems
Sep 2007
Although event tracing of parallel applications offers highly detailed performance information, tracing on current leading edge systems may lead to unacceptable perturbation of the target program...
Provided by Springer Science+Business Media
-
White Papers
Energy Efficient Packet Classification Hardware Accelerator
Mar 2008
Packet classification is an important function in a router's line-card. Although many excellent solutions have been proposed in the past, implementing high speed packet classification reaching up...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
System-Level, Thermal-Aware, Fully-Loaded Process Scheduling
Mar 2008
Processor power consumption produces significant heat and can result in higher average operating temperatures. High operating temperatures can lead to reduced reliability and at times thermal...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
What to Make of Multicore Processors for Reliable Real-Time Systems?
Apr 2010
Now that multicore microprocessors have become a commodity, it is natural to think about employing them in all kinds of computing, including high-reliability embedded real-time systems. Appealing...
Provided by Florida State University
-
White Papers
Brute-Force Determination of Multiprocessor Schedulability for Sets of Sporadic Hard-Deadline Tasks
Jun 2007
This paper describes a necessary and sufficient test for the schedulability of a set of sporadic hard-deadline tasks on a multiprocessor platform, using any of a variety of scheduling policies...
Provided by Florida State University
-
White Papers
QP: A Heterogeneous Multi-Accelerator Cluster
Mar 2009
The authors present a heterogeneous multi-accelerator cluster developed and deployed at NCSA. The cluster consists of 16 AMD dual-core CPU compute nodes each with four NVIDIA GPUs and one Xilinx...
Provided by University of Illinois
-
White Papers
Evaluation of Two-Electron Repulsion Integrals Over Gaussian Basis Functions on SRC-6 Reconfigurable Computer
Oct 2008
The authors demonstrate an implementation of the two-electron repulsion integrals code for the direct self-consistent field calculations on a reconfigurable computer. They analyze different...
Provided by University of Illinois
-
White Papers
NBTI-Aware Dynamic Instruction Scheduling
Mar 2009
NBTI is an important emerging silicon reliability problem. In this paper the authors explore a microarchitecture-level approach to mitigate NBTI related failures in the functional units of a...
Provided by University of Virginia
-
White Papers
Modeling and Analyzing NBTI in the Presence of Process Variation
Dec 2010
With continuous scaling of transistors in each technology generation, NBTI and Process Variation (PV) have become very important silicon reliability problems for the microprocessor industry. In...
Provided by University of Virginia
-
White Papers
A Benchmark Suite for Unstructured Data Processing
Nov 2007
A large fraction of the data that will stored and accessed in future systems is expected to be unstructured, in the form of images, audio files, etc. Therefore, it is very important to design...
Provided by University of Virginia
-
White Papers
Medium-Grain Cells for Reconfigurable DSP Hardware
Jun 2007
Reconfigurable hardware contains an array of programmable cells and interconnection structures. Field-programmable gate arrays use fine-grain cells that implement simple logic functions. Some...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Reducing Power in Memory Decoders by Means of Selective Precharge Schemes
May 2007
Two novel memory decoder designs for reducing energy consumption and delay are presented in this paper. These two decoding schemes are compared to the conventional NOR decoder. Fewer word lines...
Provided by Washington State University
-
White Papers
Representative Multiprogram Workloads for Multithreaded Processor Simulation
Jan 2011
Almost all new consumer-grade processors are capable of executing multiple programs simultaneously. The analysis of multiprogrammed workloads for multicore and SMT processors is challenging and...
Provided by University of California
-
White Papers
Criticality-Based Optimizations for Efficient Load Processing
Feb 2009
Some instructions have more impact on processor performance than others. Identification of these critical instructions can be used to modify and improve instruction processing. Previous work has...
Provided by Georgia Institute of Technology
-
White Papers
Thermal Optimization in Multi-Granularity Multi-Core Floorplanning
Jan 2009
Multi-core microarchitectures require a careful balance between many competing objectives to achieve the highest possible performance. Integrated Early Analysis is the consideration of all of...
Provided by Georgia Institute of Technology
-
White Papers
The Cost of Uncore in Throughput-Oriented Many-Core Processors
Jun 2008
Achieving performance through traditional techniques such as extracting more instruction level parallelism or increasing clock frequencies are losing their effectiveness due to the power wall....
Provided by Georgia Institute of Technology
-
White Papers
Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors
Mar 2008
3D integration technology greatly increases transistor density while providing faster on-chip communication. 3D implementations of processors can simultaneously provide both latency and power...
Provided by Georgia Institute of Technology
-
White Papers
Cache Vulnerability Equations for Protecting Data in Embedded Processor Caches From Soft Errors
Apr 2010
Continuous technology scaling has brought one to a point, where transistors have become extremely susceptible to cosmic radiation strikes, or soft errors. Inside the processor, caches are most...
Provided by Association for Computing Machinery
-
White Papers
Code Transformations for TLB Power Reduction
Dec 2009
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB though small is...
Provided by Springer Science+Business Media
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White Papers
A Software Solution for Dynamic Stack Management on Scratch Pad Memory
Nov 2008
In an effort to make processors more power efficient Scratch Pad Memory (SPM) have been proposed instead of caches, which can consume majority of processor power. However, application mapping on...
Provided by Arizona State University
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White Papers
Hiding Cache Miss Penalty Using Priority-Based Execution for Embedded Processors
Nov 2007
The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-end processors can...
Provided by Seoul National University
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White Papers
NWSLite: A General-Purpose, 32 Nonparametric Prediction Utility for Embedded Systems
Apr 2008
Time series-based prediction methods have a wide range of uses in embedded systems. Many OS algorithms and applications require accurate prediction of demand and supply of resources. However,...
Provided by Association for Computing Machinery
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White Papers
Dynamically Managed Multithreaded Reconfigurable Architectures for Chip Multiprocessors
Sep 2010
Prior work has demonstrated that reconfigurable logic can significantly benefit certain applications. However, reconfigurable architectures have traditionally suffered from high area overhead and...
Provided by Association for Computing Machinery
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White Papers
Enabling Parallelization Via a Reconfigurable Chip Multiprocessor
May 2010
While reconfigurable computing has traditionally involved attaching a reconfigurable fabric to a single processor core, the prospect of large-scale CMPs calls for a reevaluation of reconfigurable...
Provided by Cornell University
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White Papers
Dynamic Software Updates for Real-Time Systems
Oct 2009
Seamlessly updating software in running systems has recently gained momentum. Dynamically updating the software of real-time embedded systems, however, still poses numerous challenges: such...
Provided by Association for Computing Machinery
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White Papers
An Online Optimization-Based Technique for Dynamic Resource Allocation in GPS Servers
Jan 2011
Since web workloads are known to vary dynamically with time, in this paper, the authors argue that dynamic resource allocation techniques are necessary in the presence of such workloads to provide...
Provided by University of Massachusetts
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White Papers
Pre-Analyzed Resource and Time Provisioning in Distributed Real-Time Systems: An Application to Mobile Robotics
Jan 2011
The work is motivated by mobile robotic applications where a team of autonomous robots cooperate in achieving a goal, e.g., using sensor feeds to locate trapped humans in a building on fire. To...
Provided by University of Massachusetts
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White Papers
Quanto: Tracking Energy in Networked Embedded Systems
Oct 2008
This paper presents Quanto, a network-wide time and energy profiler for embedded network devices. By combining well-defined interfaces for hardware power states, fast high-resolution energy...
Provided by Stanford University
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White Papers
Cross-Component Energy Management: Joint Adaptation of Processor and Memory
Sep 2007
Researchers have proposed the use of adaptation to reduce the energy consumption of different hardware components, such as the processor, memory, disk, and display for general-purpose...
Provided by Association for Computing Machinery
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White Papers
Statistical Fault Injection
Mar 2008
It is well known that soft errors in logic are a concern in modern VLSI circuits. Recent studies on the IBM POWER6 microprocessor using particle-beam irradiation and full core Statistical Fault...
Provided by University of Illinois at Urbana Champaign
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White Papers
MSWAT: Low-Cost Hardware Fault Detection and Diagnosis for Multicore Systems
Oct 2009
Continued technology scaling is resulting in systems with billions of devices. Unfortunately, these devices are prone to failures from various sources, resulting in even commodity systems being...
Provided by Association for Computing Machinery
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Whitepapers
A New Reduced Clock Power Flip-Flop for Future SOC Applications
Aug 2012
In this paper a novel technique is proposed based on the comparison between Conventional Conditional Data Mapping Flip-flop and Clock Pair Shared D Flip Flop (CPSFF) here the authors are checking...
Provided by IJCTT-International Journal of Computer Trends and Technology
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Whitepapers
Implementation of SOBEL Edge Detection on FPGA
Jun 2012
The image processing algorithms has been limited to software implementation which is slower due to the limited processor speed. So, a dedicated processor for edge detection is required which was...
Provided by IJCTT-International Journal of Computer Trends and Technology
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White Papers
The Standard of Embedded World by Studying of OSEK/VDX
Feb 2011
This paper will describe the concept of a real-time operating system, capable of multitasking, which can be used for motor vehicles. Embedded systems are characterized by stringent real-time...
Provided by Kyungpook National University
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