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Mission Statement
TechRepublic's ITPapers is the Web's largest library of free technical IT white papers, webcasts, and case studies. Covering IT categories including Data Management, IT Management, Networking, Communications, Enterprise Applications, Storage, Security and much more, TechRepublic's White Paper Directory is the best source for technical white papers and IT information.
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White Papers
Demand Code Paging for NAND Flash in MMU-Less Embedded Systems
Dec 2010
NAND flash is preferred for code and data storage in embedded devices due to its high density and low cost. However, NAND flash requires code to be copied to main memory for execution. In...
Provided by University of Pittsburgh
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White Papers
Display Power Management Policies in Practice
Jun 2010
The authors present the first study of the real-world behavior of Display Power Management (DPM) policies. DPM policies control the mechanism of powering on and off the display - turning off the...
Provided by Association for Computing Machinery
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White Papers
Pulsed Multi-Layered Image Filtering: A VLSI Implementation
Jun 2009
Image convolution similar to the receptive fields found in mammalian visual pathways has long been used in conventional image processing in the form of Gabor masks. However, no VLSI implementation...
Provided by Dresden University of Technology
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White Papers
An Analysis of Delay Based PUF Implementations on FPGA
Mar 2010
Physical Unclonable Functions promise cheap, efficient, and secure identification and authentication of devices. In FPGA devices, PUFs may be instantiated directly from FPGA fabric components in...
Provided by Springer Science+Business Media
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White Papers
Improved Ring Oscillator PUF: An FPGA-Friendly Secure Primitive
Oct 2010
In this paper, the authors analyze Ring Oscillator (RO) based Physical Unclonable Function (PUF) on FPGAs. They show that the systematic process variation adversely affects the ability of the...
Provided by International Association for Cryptologic Research
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White Papers
DMP: Deterministic Shared Memory Multiprocessing
Mar 2009
Current shared memory multicore and multiprocessor systems are nondeterministic. Each time these systems execute a multithreaded application, even if supplied with the same input, they can produce...
Provided by Association for Computing Machinery
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White Papers
Polymorphic On-Chip Networks
Mar 2008
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. The authors begin this...
Provided by University of Washington
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White Papers
DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Efficiently
Mar 2008
Support for deterministic replay of multithreaded execution can greatly help in finding concurrency bugs. For highest effectiveness, replay schemes should record at production-run speed, keep...
Provided by University of Illinois
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White Papers
Crafting a Usable Microkernel, Processor, and I/O System With Strict and Provable Information Flow Security
Mar 2011
High assurance systems used in avionics, medical implants, and cryptographic devices often rely on a small trusted base of hardware and software to manage the rest of the system. Crafting the core...
Provided by Association for Computing Machinery
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White Papers
HLS: Combining Statistical and Symbolic Simulation to Guide Microprocessor Designs
Nov 2009
As microprocessors continue to evolve many optimizations reach a point of diminishing returns. The authors introduce HLS, a hybrid processor simulator which uses statistical models and symbolic...
Provided by UC Regents
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White Papers
Quantifying the Sub-Optimality of Uniprocessor Fixed Priority Pre-Emptive Scheduling for Sporadic Tasksets With Arbitrary Deadlines
Jan 2010
In this paper, the authors are interested in determining the largest factor by which the processing speed of a uniprocessor would need to be increased, such that any feasible taskset (that was...
Provided by University of York
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White Papers
On Optimal Priority Assignment for Response Time Analysis of Global Fixed Priority Pre-Emptive Scheduling in Multiprocessor Hard Real-Time Systems
Apr 2010
This paper investigates the problem of optimal priority assignment in multiprocessor real-time systems using global fixed task-priority pre-emptive scheduling. Previous work in this area showed...
Provided by University of York
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White Papers
FPZL Schedulability Analysis
Jun 2010
This paper presents the FPZL scheduling algorithm for multiprocessor real-time systems. FPZL is similar to global fixed priority pre-emptive scheduling; however, whenever a task reaches a state of...
Provided by University of York
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White Papers
Improved Schedulability Analysis For Multiprocessor Systems With Resource Sharing
Jun 2010
This paper presents the recent efforts to close the gap between the state-of-the-art homogeneous (or identical) multiprocessor and uniprocessor schedulability analyses in the context of resource...
Provided by University of York
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White Papers
Practical Approach to Programmable Analog Circuits With Memristors
Jan 2010
The authors suggest an approach to use memristors (resistors with memory) in programmable analog circuits. The idea consists in a circuit design in which low voltages are applied to memristors...
Provided by University of South Carolina
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White Papers
Sensitivity Analysis for Real-Time Systems
Mar 2009
The correctness of a real-time system depends on not only the running results but also on the time at which results are produced. A hard real-time system is required to complete the operations...
Provided by University of York
-
White Papers
The Scratchpad Memory Management Unit for Microblaze: Implementation, Testing, and Case Study
Apr 2009
This paper proposes the Scratchpad Memory Management Unit (SMMU) to act as a perfect data cache for a known subset of the data used by a program. This enables the execution time for each load or...
Provided by University of York
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White Papers
Priority Assignment for Global Fixed Priority Pre-Emptive Scheduling in Multiprocessor Real-Time Systems
May 2009
This paper addresses the problem of priority assignment in multiprocessor real-time systems using global fixed task-priority pre-emptive scheduling. In this paper, the authors prove that Audsley's...
Provided by University of York
-
White Papers
Towards Bandwidth Optimal Temporal Partitioning
Aug 2009
In real-time systems the available processing time is partitioned in order to enforce separation of concerns of concurrent application components. This is a necessary step to prevent possible side...
Provided by University of York
-
White Papers
A Survey of Hard Real-Time Scheduling Algorithms and Schedulability Analysis Techniques for Multiprocessor Systems
Nov 2009
This survey covers hard real-time scheduling algorithms and schedulability analysis techniques for homogeneous multiprocessor systems. It reviews the key results in this field from its origins in...
Provided by University of York
-
White Papers
Schedulability Analysis for Real-Time Systems With EDF Scheduling
Feb 2008
Real-time scheduling is the theoretical basis of real-time systems engineering. Earliest Deadline First (EDF) is an optimal scheduling algorithm for uniprocessor real-time systems. The existing...
Provided by University of York
-
White Papers
Utilization Based Spare Capacity Distribution
Feb 2008
Flexible real-time applications have predefined temporal limits within which they can operate. Real-time systems that support flexible scheduling need a mechanism to distribute spare capacity in a...
Provided by University of York
-
White Papers
WCET-Aware Optimization of Shared Cache Partition and Bus Arbitration for Hard Real-Time Multicore Systems
May 2011
In recent years, multicore processors have been receiving a significant amount of attention from avionic and automotive industries as the demand for high-end real-time applications drastically...
Provided by University of Illinois
-
White Papers
Indirect Mappings of Multi-Touch Input Using One and Two Hands
Apr 2008
Touchpad and touchscreen interaction using multiple fingers is emerging as a valuable form of high-degree-of-freedom input. While bimanual interaction has been extensively studied, touchpad...
Provided by Association for Computing Machinery
-
White Papers
Comparing Gesture and Touch for Notification System Interactions
Nov 2008
The authors explore some of the characteristics of multimodal input interaction spaces for notification systems within a multi-tasking environment like a command and control center using two...
Provided by Virginia Tech
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White Papers
Back-of-Device Interaction Allows Creating Very Small Touch Devices
Sep 2008
In this paper, the authors explore how to add pointing input capabilities to very small screen devices. On first sight, touchscreens seem to allow for particular compactness, because they...
Provided by Association for Computing Machinery
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White Papers
Efficient Power Modeling and Software Thermal Sensing for Runtime Temperature Monitoring
Aug 2007
The evolution of microprocessors has been hindered by increasing power consumption and heat dissipation on die. An excessive amount of heat creates reliability problems, reduces the lifetime of a...
Provided by Association for Computing Machinery
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White Papers
Integrating Dynamic Power Management in Systems With Multiple DVS Components
Jan 2011
Recent embedded computing platforms offer multiple independent clocks for different components involved in processing a single instruction stream, such as CPU and memory, giving rise to a new...
Provided by University of Illinois
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White Papers
A Fault Tolerance Protocol for Fast Recovery
Feb 2008
Large machines with tens or even hundreds of thousands of processors are currently in use. As the number of components increases, the mean time between failure will decrease further. Fault...
Provided by University of Illinois
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White Papers
A Method to Solve the Probe Load Effection in the High Speed Digital Circuit
Jun 2009
The measuring result has much business with the performance of the oscilloscope probe. First the authors analyze the probe load effection, and then present a method to solve the problem by using...
Provided by Tianjin Polytechnic University
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White Papers
An Efficient Hardware Implementation of Extended and Fast Physical Addressing in Microprocessor-Based Systems Using Programmable Logic
Jun 2009
This paper describes an efficient hardware implementation of a new technique for interfacing the data exchange between the microprocessor-based systems and the external devices. This technique,...
Provided by University SAAD Dahlab Blida
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White Papers
Interval Analysis Applied to Model-Checking of Embedded Control Systems
May 2008
Model-checking is a search technique that explores the state space of a modeled system looking for states that match specific criteria. The criteria can be anything from simple assertions to...
Provided by University of York
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White Papers
Schedulability Analysis for a Real-Time Multiprocessor System Based on Service Contracts and Resource Partitioning
Oct 2009
This paper presents some initial results of the research which addresses the increasing gaps between the power of multicore/multiprocessor systems and the lack of development models and tools that...
Provided by University of York
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White Papers
Improvement to Quick Processor-Demand Analysis for EDF-Scheduled Real-Time Systems
Sep 2008
Earliest Deadline First (EDF) is an optimal scheduling algorithm for uniprocessor real-time systems. Quick Processor-demand Analysis (QPA) provides efficient and exact schedulability tests for EDF...
Provided by University of York
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White Papers
Run Time Detection of Timing Errors in Real-Time Systems
Oct 2008
Real-time systems comprise a class of computing systems whose functionality is interrelated to the timing constraints of the system, which are normally specified by deadlines. In order to...
Provided by University of York
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White Papers
CASL: A Rapid-Prototyping Language for Modern Micro-Architectures
Feb 2009
The authors introduce CASL, the CoGenT Architecture Specification Language, a mixed behavioral-structure architecture description language designed to facilitate fast-prototyping and tool...
Provided by University of Massachusetts Amherst
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White Papers
Evaluating GPUs for Network Packet Signature Matching
Feb 2009
Modern network devices employ deep packet inspection to enable sophisticated services such as intrusion detection, traffic shaping, and load balancing. At the heart of such services is a signature...
Provided by University of Wisconsin
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White Papers
Hard Data on Soft Errors: A Large-Scale Assessment of Real-World Error Rates in GPGPU
Nov 2009
Graphics Processing Units (GPUs) are gaining widespread use in computational chemistry and other scientific simulation contexts because of their huge performance advantages relative to...
Provided by Stanford University
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White Papers
Latency Characteristics of Event-Driven Task Scheduler Embedded in Neuron Chip
Dec 2007
The paper presents the experimental measurements of the temporal measures of the task scheduler embedded in Neuron Chip microcontroller. The investigated task scheduler dynamically manages sharing...
Provided by AGH University of Science and Technology
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White Papers
Test Case Generation for Context Testing of Embedded Systems
Nov 2007
The context of a modular system through which its embedded components interact with the user is the main development target of the modular system because developers usually purchase embedded...
Provided by Kumoh National Institute of Technology
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White Papers
Automatic Amortised Worst-Case Execution Time Analysis
Nov 2007
The authors' research focuses on formally bounded WCET analysis, where they aim to provide absolute guarantees on execution time bounds. In this paper, they describe how amortisation can be used...
Provided by University of St Andrews
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White Papers
Worst-Case Execution Time Analysis Through Types
Jun 2009
construct a fully automatic static WCET analysis suitable for real-time embedded systems applications by augmenting a high-level static analysis technique (originally aimed at heap-space) with a...
Provided by Heriot-Watt University
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White Papers
Analyzing Schedulability of Energy-oriented Distributed Real-time Embedded Software
Sep 2011
As computer systems become increasingly inter-networked, most of critical systems are Distributed Real-time Embedded (DRE) system. A challenging problem faced by researchers and developers of DRE...
Provided by Academy Publisher
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White Papers
Using Property-Based Oracles When Testing Embedded System Applications
Jan 2011
Embedded systems are becoming increasingly ubiquitous, controlling a wide variety of popular and safety-critical devices. Effective testing techniques could improve the dependability of these...
Provided by University of Nebraska - Lincoln
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White Papers
Process Oriented Device Driver Development
Dec 2008
Operating systems are the core software component of many modern computer systems, ranging from small specialized embedded systems through to large distributed operating systems. The demands...
Provided by John Wiley & Sons
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White Papers
Contour Guided Dissemination for Networked Embedded Systems
Nov 2009
Networked Embedded Systems have come to occupy an important role in emerging applications. Nodes in such a system are interconnected by a mesh topology. Despite the availability of multiple...
Provided by Taylor & Francis Group
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White Papers
3D Integration of CMOL Structures for FPGA Applications
Sep 2009
In this paper, a novel three-dimensional CMOS-nano hybrid technology, 3D CMOL, is introduced to establish FPGA chips. By combining two leading technologies, hybrid CMOS/nanoelectronic circuit...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Three-Dimensional CMOL: Three-Dimensional Integration of CMOS/nanomaterial Hybrid Digital Circuits
Jul 2007
The CMOS molecular (CMOL) circuit is a promising hybrid structure incorporating the nanowire crossbar into the CMOS Integrated Circuit (IC) implementation. In this letter, a novel...
Provided by Institution of Engineering and Technology
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White Papers
Design and Implementation of Modular FPGA-Based PID Controllers
Aug 2007
In this paper, modular design of embedded feedback controllers using Field-Programmable Gate Array (FPGA) technology is studied. To this end, a novel Distributed-Arithmetic (DA)-based Proportional...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
A Requirements Specification Template of a Communication Network Based on CAN Protocol to Automotive Embedded Systems
Oct 2010
This paper presents the results of studies that made possible to propose a particular contribution to improve the quality on developing automotive embedded systems through a requirements...
Provided by Universidade Metodista de Piracicaba
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White Papers
Reduced Computational Cost in the Calculation of Worst Case Response Time for Real Time Systems
Oct 2009
Modern Real Time Operating Systems require reducing computational costs even though the microprocessors become more powerful each day. It is usual that Real Time Operating Systems for embedded...
Provided by Universidad Nacional del Sur
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White Papers
Memory Disambiguation Hardware: A Review
Oct 2008
One of the main challenges of modern processor designs is the implementation of scalable and efficient mechanisms to detect memory access order violations as a result of out-of-order execution....
Provided by Universidad Complutense de Madrid
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White Papers
StageNet: A Reconfigurable CMP Fabric for Resilient Systems
Nov 2007
Though CMOS feature size scaling has been the source of dramatic performance gains, this scaling has lead to mounting reliability concerns due to increasing power densities and on-chip...
Provided by University of Michigan
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White Papers
The StageNet Fabric for Constructing Resilient Multicore Systems
Sep 2008
Scaling of CMOS feature size has long been a source of dramatic performance gains. However, the reduction in voltage levels has not been able to match this rate of scaling, leading to increasing...
Provided by University of Michigan
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White Papers
StageWeb: Interweaving Pipeline Stages into a Wearout and Variation Tolerant CMP Fabric
Jun 2010
Manufacture-time process variation and life-time failure projections have become a major industry concern. Consequently, fault tolerance, historically of interest only for mission-critical...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
StageNetSlice: A Reconfigurable Microarchitecture Building Block for Resilient CMP Systems
Oct 2008
Although CMOS feature size scaling has been the source of dramatic performance gains, it has lead to mounting reliability concerns due to increasing power densities and on-chip temperatures. Given...
Provided by Association for Computing Machinery
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White Papers
Parallelizing Sequential Applications on Commodity Hardware Using a Low-Cost Software Transactional Memory
Jun 2009
Multicore designs have emerged as the mainstream design paradigm for the microprocessor industry. Unfortunately, providing multiple cores does not directly translate into performance for most...
Provided by Association for Computing Machinery
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White Papers
Data Access Partitioning for Fine-Grain Parallelism on Multicore Architectures
Jan 2012
The recent design shift towards multicore processors has spawned a significant amount of research in the area of program parallelization. The future abundance of cores on a single chip requires...
Provided by University of Michigan
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White Papers
BulletProof: A DefectÂTolerant CMP Switch Architecture
Jan 2012
As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transient errors, and...
Provided by University of Michigan
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White Papers
Selfcalibrating Online Wearout Detection
Jan 2011
Technology scaling, characterized by decreasing feature size, thinning gate oxide, and non-ideal voltage scaling, will become a major hindrance to microprocessor reliability in future technology...
Provided by University of Michigan
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White Papers
MacroSS: Macro-SIMDization of Streaming Applications
Mar 2010
SIMD (Single Instruction, Multiple Data) engines are an essential part of the processors in various computing markets, from servers to the embedded domain. Although SIMD-enabled architectures have...
Provided by Association for Computing Machinery
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White Papers
Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-Thread Applications
Jan 2012
Chip multiprocessors with multiple simpler cores are gaining popularity because they have the potential to drive future performance gains without exacerbating the problems of power dissipation and...
Provided by University of Michigan
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White Papers
Power-Efficient Medical Image Processing Using PUMA
Jun 2009
Graphics Processing Units (GPUs) are becoming an increasingly popular platform to run applications that require a high computation throughput. They are limited, however, by memory bandwidth and...
Provided by University of Michigan
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White Papers
Low-Power Scientific Computing
Dec 2009
Scientists and mathematicians are increasingly realizing the computational benefits of using modern, multi-core architectures. In response to this, manufacturers of traditional desktop...
Provided by University of Michigan
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White Papers
Modulo Scheduling for Highly Customized Datapaths to Increase Hardware Reusability
Apr 2008
In the embedded domain, custom hardware in the form of ASICs is often used to implement critical parts of applications when performance and energy efficiency goals cannot be met with software...
Provided by Association for Computing Machinery
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White Papers
PEPSC: A Power-Efficient Processor for Scientific Computing
Oct 2011
The rapid advancements in the computational capabilities of the Graphics Processing Unit (GPU) as well as the deployment of general programming models for these devices have made the vision of a...
Provided by University of Michigan
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White Papers
Enabling Ultra Low Voltage System Operation by Tolerating On-Chip Cache Failures
Aug 2009
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely used technique to...
Provided by Association for Computing Machinery
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White Papers
Necromancer: Enhancing System Throughput by Animating Dead Cores
Jun 2010
Aggressive technology scaling into the nanometer regime has led to a host of reliability challenges in the last several years. Unlike on-chip caches, which can be efficiently protected using...
Provided by Association for Computing Machinery
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White Papers
Archipelago: A Polymorphic Cache Design for Enabling Robust Near-Threshold Operation
Dec 2010
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely used technique to...
Provided by Association for Computing Machinery
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White Papers
MiBench: A Free, Commercially Representative Embedded Benchmark Suite
Jan 2011
This paper examines a set of commercially representative embedded programs and compares them to an existing benchmark suite, SPEC2000. A new version of SimpleScalar that has been adapted to the...
Provided by University of Michigan
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White Papers
Modeling and Characterizing Power Variability in Multicore Architectures
Dec 2008
Parameter variation due to manufacturing error will be an unavoidable consequence of technology scaling in future generations. The impact of random variation in physical factors such as gate...
Provided by Northwestern University
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White Papers
Exploiting Locality to Improve Circuit-Level Timing Speculation
Oct 2009
Circuit-level timing speculation has been proposed as a technique to reduce dependence on design margins, eliminating power and performance overheads. Recent work has proposed micro-architectural...
Provided by Northwestern University
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White Papers
Instruction-Driven Clock Scheduling With Glitch Mitigation
Aug 2008
Instruction-driven clock scheduling is a mechanism that minimizes clock power in deeply-pipelined datapaths. Analysis of realistic processor workloads shows a preponderance of bubbles persist...
Provided by Association for Computing Machinery
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White Papers
Energy-And Area-Efficient Architectures Through Application Clustering and Architectural Heterogeneity
Mar 2009
Customizing architectures for particular applications is a promising approach to yield highly energy-efficient designs for embedded systems. This paper explores the benefits of architectural...
Provided by Association for Computing Machinery
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White Papers
Design and Test Strategies for Microarchitectural Post-Fabrication Tuning
Aug 2009
Process variations are a major hurdle for continued technology scaling. Both systematic and random variations will affect the critical delay of fabricated chips, causing a wide frequency and power...
Provided by Stanford University
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White Papers
Tribeca: Design for PVT Variations With Local Recovery and Fine-Grained Adaptation
Dec 2009
With continued advances in CMOS technology, parameter variations are emerging as a major design challenge. Irregularities during the fabrication of a microprocessor and variations of voltage and...
Provided by Association for Computing Machinery
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White Papers
Eliminating Voltage Emergencies Via Software-Guided Code Transformations
Aug 2010
In recent years, circuit reliability in modern high-performance processors has become increasingly important. Shrinking feature sizes and diminishing supply voltages have made circuits more...
Provided by University of Virginia
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White Papers
An Analysis of On-Chip Interconnection Networks for Large-Scale Chip Multiprocessors
Apr 2010
With the number of cores of Chip MultiProcessors (CMPs) rapidly growing as technology scales down, connecting the different components of a CMP in a scalable and efficient way becomes increasingly...
Provided by Association for Computing Machinery
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White Papers
On the Power Dissipation of Embedded Memory Blocks Used to Implement Logic in Field-Programmable Gate Arrays
Jan 2008
The authors investigate the power and energy implications of using embedded FPGA memory blocks to implement logic. Previous studies have shown that this technique provides extremely dense...
Provided by Hindawi Publishing
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White Papers
A Game-Theoretic Approach for Run-Time Distributed Optimization on MP-SoC
Aug 2008
With forecasted hundreds of Processing Elements (PEs), future embedded systems will be able to handle multiple applications with very diverse running constraints. Systems will integrate...
Provided by Hindawi Publishing
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White Papers
Pulsed Multi-Layered Image Filtering: A VLSI Implementation
Jun 2009
Image convolution similar to the receptive fields found in mammalian visual pathways has long been used in conventional image processing in the form of Gabor masks. However, no VLSI implementation...
Provided by Dresden University of Technology
-
White Papers
An Analysis of Delay Based PUF Implementations on FPGA
Mar 2010
Physical Unclonable Functions promise cheap, efficient, and secure identification and authentication of devices. In FPGA devices, PUFs may be instantiated directly from FPGA fabric components in...
Provided by Springer Science+Business Media
-
White Papers
Improved Ring Oscillator PUF: An FPGA-Friendly Secure Primitive
Oct 2010
In this paper, the authors analyze Ring Oscillator (RO) based Physical Unclonable Function (PUF) on FPGAs. They show that the systematic process variation adversely affects the ability of the...
Provided by International Association for Cryptologic Research
-
White Papers
DMP: Deterministic Shared Memory Multiprocessing
Mar 2009
Current shared memory multicore and multiprocessor systems are nondeterministic. Each time these systems execute a multithreaded application, even if supplied with the same input, they can produce...
Provided by Association for Computing Machinery
-
White Papers
Polymorphic On-Chip Networks
Mar 2008
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. The authors begin this...
Provided by University of Washington
-
White Papers
DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Efficiently
Mar 2008
Support for deterministic replay of multithreaded execution can greatly help in finding concurrency bugs. For highest effectiveness, replay schemes should record at production-run speed, keep...
Provided by University of Illinois
-
White Papers
Crafting a Usable Microkernel, Processor, and I/O System With Strict and Provable Information Flow Security
Mar 2011
High assurance systems used in avionics, medical implants, and cryptographic devices often rely on a small trusted base of hardware and software to manage the rest of the system. Crafting the core...
Provided by Association for Computing Machinery
-
White Papers
HLS: Combining Statistical and Symbolic Simulation to Guide Microprocessor Designs
Nov 2009
As microprocessors continue to evolve many optimizations reach a point of diminishing returns. The authors introduce HLS, a hybrid processor simulator which uses statistical models and symbolic...
Provided by UC Regents
-
White Papers
Quantifying the Sub-Optimality of Uniprocessor Fixed Priority Pre-Emptive Scheduling for Sporadic Tasksets With Arbitrary Deadlines
Jan 2010
In this paper, the authors are interested in determining the largest factor by which the processing speed of a uniprocessor would need to be increased, such that any feasible taskset (that was...
Provided by University of York
-
White Papers
On Optimal Priority Assignment for Response Time Analysis of Global Fixed Priority Pre-Emptive Scheduling in Multiprocessor Hard Real-Time Systems
Apr 2010
This paper investigates the problem of optimal priority assignment in multiprocessor real-time systems using global fixed task-priority pre-emptive scheduling. Previous work in this area showed...
Provided by University of York
-
White Papers
FPZL Schedulability Analysis
Jun 2010
This paper presents the FPZL scheduling algorithm for multiprocessor real-time systems. FPZL is similar to global fixed priority pre-emptive scheduling; however, whenever a task reaches a state of...
Provided by University of York
-
White Papers
Improved Schedulability Analysis For Multiprocessor Systems With Resource Sharing
Jun 2010
This paper presents the recent efforts to close the gap between the state-of-the-art homogeneous (or identical) multiprocessor and uniprocessor schedulability analyses in the context of resource...
Provided by University of York
-
White Papers
Practical Approach to Programmable Analog Circuits With Memristors
Jan 2010
The authors suggest an approach to use memristors (resistors with memory) in programmable analog circuits. The idea consists in a circuit design in which low voltages are applied to memristors...
Provided by University of South Carolina
-
White Papers
Sensitivity Analysis for Real-Time Systems
Mar 2009
The correctness of a real-time system depends on not only the running results but also on the time at which results are produced. A hard real-time system is required to complete the operations...
Provided by University of York
-
White Papers
The Scratchpad Memory Management Unit for Microblaze: Implementation, Testing, and Case Study
Apr 2009
This paper proposes the Scratchpad Memory Management Unit (SMMU) to act as a perfect data cache for a known subset of the data used by a program. This enables the execution time for each load or...
Provided by University of York
-
White Papers
Priority Assignment for Global Fixed Priority Pre-Emptive Scheduling in Multiprocessor Real-Time Systems
May 2009
This paper addresses the problem of priority assignment in multiprocessor real-time systems using global fixed task-priority pre-emptive scheduling. In this paper, the authors prove that Audsley's...
Provided by University of York
-
White Papers
Towards Bandwidth Optimal Temporal Partitioning
Aug 2009
In real-time systems the available processing time is partitioned in order to enforce separation of concerns of concurrent application components. This is a necessary step to prevent possible side...
Provided by University of York
-
White Papers
A Survey of Hard Real-Time Scheduling Algorithms and Schedulability Analysis Techniques for Multiprocessor Systems
Nov 2009
This survey covers hard real-time scheduling algorithms and schedulability analysis techniques for homogeneous multiprocessor systems. It reviews the key results in this field from its origins in...
Provided by University of York
-
White Papers
Schedulability Analysis for Real-Time Systems With EDF Scheduling
Feb 2008
Real-time scheduling is the theoretical basis of real-time systems engineering. Earliest Deadline First (EDF) is an optimal scheduling algorithm for uniprocessor real-time systems. The existing...
Provided by University of York
-
White Papers
Utilization Based Spare Capacity Distribution
Feb 2008
Flexible real-time applications have predefined temporal limits within which they can operate. Real-time systems that support flexible scheduling need a mechanism to distribute spare capacity in a...
Provided by University of York
-
White Papers
WCET-Aware Optimization of Shared Cache Partition and Bus Arbitration for Hard Real-Time Multicore Systems
May 2011
In recent years, multicore processors have been receiving a significant amount of attention from avionic and automotive industries as the demand for high-end real-time applications drastically...
Provided by University of Illinois
-
White Papers
Indirect Mappings of Multi-Touch Input Using One and Two Hands
Apr 2008
Touchpad and touchscreen interaction using multiple fingers is emerging as a valuable form of high-degree-of-freedom input. While bimanual interaction has been extensively studied, touchpad...
Provided by Association for Computing Machinery
-
White Papers
Comparing Gesture and Touch for Notification System Interactions
Nov 2008
The authors explore some of the characteristics of multimodal input interaction spaces for notification systems within a multi-tasking environment like a command and control center using two...
Provided by Virginia Tech
-
White Papers
Back-of-Device Interaction Allows Creating Very Small Touch Devices
Sep 2008
In this paper, the authors explore how to add pointing input capabilities to very small screen devices. On first sight, touchscreens seem to allow for particular compactness, because they...
Provided by Association for Computing Machinery
-
White Papers
Efficient Power Modeling and Software Thermal Sensing for Runtime Temperature Monitoring
Aug 2007
The evolution of microprocessors has been hindered by increasing power consumption and heat dissipation on die. An excessive amount of heat creates reliability problems, reduces the lifetime of a...
Provided by Association for Computing Machinery
-
White Papers
Integrating Dynamic Power Management in Systems With Multiple DVS Components
Jan 2011
Recent embedded computing platforms offer multiple independent clocks for different components involved in processing a single instruction stream, such as CPU and memory, giving rise to a new...
Provided by University of Illinois
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White Papers
A Fault Tolerance Protocol for Fast Recovery
Feb 2008
Large machines with tens or even hundreds of thousands of processors are currently in use. As the number of components increases, the mean time between failure will decrease further. Fault...
Provided by University of Illinois
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White Papers
A Method to Solve the Probe Load Effection in the High Speed Digital Circuit
Jun 2009
The measuring result has much business with the performance of the oscilloscope probe. First the authors analyze the probe load effection, and then present a method to solve the problem by using...
Provided by Tianjin Polytechnic University
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White Papers
An Efficient Hardware Implementation of Extended and Fast Physical Addressing in Microprocessor-Based Systems Using Programmable Logic
Jun 2009
This paper describes an efficient hardware implementation of a new technique for interfacing the data exchange between the microprocessor-based systems and the external devices. This technique,...
Provided by University SAAD Dahlab Blida
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White Papers
Interval Analysis Applied to Model-Checking of Embedded Control Systems
May 2008
Model-checking is a search technique that explores the state space of a modeled system looking for states that match specific criteria. The criteria can be anything from simple assertions to...
Provided by University of York
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White Papers
Schedulability Analysis for a Real-Time Multiprocessor System Based on Service Contracts and Resource Partitioning
Oct 2009
This paper presents some initial results of the research which addresses the increasing gaps between the power of multicore/multiprocessor systems and the lack of development models and tools that...
Provided by University of York
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White Papers
Improvement to Quick Processor-Demand Analysis for EDF-Scheduled Real-Time Systems
Sep 2008
Earliest Deadline First (EDF) is an optimal scheduling algorithm for uniprocessor real-time systems. Quick Processor-demand Analysis (QPA) provides efficient and exact schedulability tests for EDF...
Provided by University of York
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White Papers
Run Time Detection of Timing Errors in Real-Time Systems
Oct 2008
Real-time systems comprise a class of computing systems whose functionality is interrelated to the timing constraints of the system, which are normally specified by deadlines. In order to...
Provided by University of York
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White Papers
CASL: A Rapid-Prototyping Language for Modern Micro-Architectures
Feb 2009
The authors introduce CASL, the CoGenT Architecture Specification Language, a mixed behavioral-structure architecture description language designed to facilitate fast-prototyping and tool...
Provided by University of Massachusetts Amherst
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White Papers
Evaluating GPUs for Network Packet Signature Matching
Feb 2009
Modern network devices employ deep packet inspection to enable sophisticated services such as intrusion detection, traffic shaping, and load balancing. At the heart of such services is a signature...
Provided by University of Wisconsin
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White Papers
Hard Data on Soft Errors: A Large-Scale Assessment of Real-World Error Rates in GPGPU
Nov 2009
Graphics Processing Units (GPUs) are gaining widespread use in computational chemistry and other scientific simulation contexts because of their huge performance advantages relative to...
Provided by Stanford University
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White Papers
Latency Characteristics of Event-Driven Task Scheduler Embedded in Neuron Chip
Dec 2007
The paper presents the experimental measurements of the temporal measures of the task scheduler embedded in Neuron Chip microcontroller. The investigated task scheduler dynamically manages sharing...
Provided by AGH University of Science and Technology
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White Papers
Test Case Generation for Context Testing of Embedded Systems
Nov 2007
The context of a modular system through which its embedded components interact with the user is the main development target of the modular system because developers usually purchase embedded...
Provided by Kumoh National Institute of Technology
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White Papers
A Development of Disk Drive With Flash Memory for ATA-6
Sep 2007
In this paper, the authors have designed and constructed a flash memory drive using the ATA-6 bus method for flash memories, which is an element of semiconductors, in order to improve the problems...
Provided by Cheongju University
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White Papers
The Importance of Including Dependencies in Trace Based Performance Analysis of On-Chip Networks
Dec 2009
With the advent of large scale chip-level multiprocesssors, there is renewed interest in the design and analysis of on-chip networks. The use of full system simulation is the most accurate way to...
Provided by UC Regents
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