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Mission Statement
TechRepublic's ITPapers is the Web's largest library of free technical IT white papers, webcasts, and case studies. Covering IT categories including Data Management, IT Management, Networking, Communications, Enterprise Applications, Storage, Security and much more, TechRepublic's White Paper Directory is the best source for technical white papers and IT information.
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White Papers
Performance Evaluation of a Simplified Matrix Processor
Feb 2012
Data parallel applications are growing in importance and demanding increased performance from hardware. Since, the fundamental data structures for a wide variety of data-parallel applications are...
Provided by The Second International Conference on Communications and Information Technology
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White Papers
Identification of Highly Jittered Radar Emitters: Issues on Low Cost Embedded Design
Feb 2012
This paper presents efforts toward design of radar identification system for highly jittered radar emitters. The paper first provides a mathematical background of clustering techniques, and then...
Provided by The Second International Conference on Communications and Information Technology
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White Papers
Task Scheduling Algorithm to Reduce the Number of Processors Using Merge Conditions
Feb 2012
Some task scheduling algorithms generate the shortest schedule, when its input DAG satisfies a specified condition. Among those scheduling algorithms, TDS algorithm proposed a DAG condition where...
Provided by Engg Journals Publications
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White Papers
Digital Logic Embedding Using Single Row
Dec 2011
The authors present a technique to improve embedding capacity of Image using digital logic in this paper. They have applied digital logic operations on two equal halves of an image row to derive...
Provided by Engg Journals Publications
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White Papers
Energy-Aware Task Partitioning on Heterogeneous Multiprocessor Platforms
Mar 2012
Efficient task partitioning plays a crucial role in achieving high performance at multiprocessor platforms. This paper addresses the problem of energy-aware static partitioning of periodic...
Provided by International Journal of Computer Science Issues
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White Papers
Design and Implementation of Adder and Subtracter Experiments Using Virtual Intelligent SoftLab
Jan 2012
The scope of this paper includes study and implementation of Full Adder and Subtractor. A full-adder and Subtracter is composed with IC and virtual instruments. Along with the VIS model the...
Provided by International Journal of Computer Science and Telecommunications
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White Papers
Program Interferometry
Nov 2011
Modern microprocessors have many micro-architectural features. Quantifying the performance impact of one feature such as dynamic branch prediction can be difficult. On one hand, a timing simulator...
Provided by University of Texas
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White Papers
An Optimized Scaled Neural Branch Predictor
Oct 2011
Conditional branch prediction remains one of the most important enabling technologies for high-performance microprocessors. A small improvement in accuracy can result in a large improvement in...
Provided by University of Texas
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White Papers
VLSI Implementation of Fast Convolution Based 2-D Discrete Wavelet Transform for High Speed, Area Efficient Image Computing
Mar 2012
A VLSI design approach of a high speed and real-time 2-D Discrete Wavelet Transform computing is being presented in the paper. The proposed architecture, based on new and fast convolution...
Provided by International Journal of Power Control Signal and Computation (IJPCSC)
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White Papers
Blocking Misbehaving Users In Anonymizying Networks- Embedded Based
Mar 2012
Anonymizing networks such as Tor allow users to access Internet services privately by using a series of routers to hide the client's IP address from the server. The success of such networks,...
Provided by International Journal of Power Control Signal and Computation (IJPCSC)
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White Papers
Runtime CPU Scheduler Customization Framework for Real Time Operating System
Mar 2012
Most of the embedded systems have real-time requirements about the use of Real-Time Operating Systems able of satisfying the embedded system requirements. So, in embedded application where the...
Provided by International Journal of Computer Technology and Applications
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White Papers
Design and Implementation of Non Real Time and Real Time Digital Filters for Audio Signal Processing
May 2011
An analog active filter can not provide a very sharp cut-off for both higher and lower frequency component, while a Digital Signal Processor (DSP) using digital filter effectively reduces the...
Provided by Journal of Computing
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White Papers
Real Time Behavior of Data in Distributed Embedded Systems
Nov 2008
Nowadays, most embedded systems become distributed systems structured as a set of communicating components. Therefore, they display a less deterministic global behavior than centralized systems...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
A Study on the Design of Coaxial Isolator With Filter Circuit
Dec 2011
In this paper, the detailed design of the 1.8 GHz band Y-junction stripline circulator with the low pass filter circuit in the center conductor in order to higher attenuations below value of -30...
Provided by Dongguk University
-
White Papers
Implementation of Area Efficient Memory-Based FIR Digital Filter Using LUT-Multiplier
Mar 2012
Memory based structures are well-suited for many Digital Signal Processing (DSP) applications, which involve multiplication with a fixed set of coefficients. Memory-based structures are more...
Provided by International Journal of Computer Science and Information Technologies
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White Papers
Integrating Logic Analyzer Functionality Into VHDL Designs
Jan 2012
A combined hardware and software system for the debugging of FPGA designs is designed. It provides a powerful logic analyzer implemented as a fully parameterized VHDL description. The system can...
Provided by International Journal of Computer Science and Information Technologies
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White Papers
Design and Implementation of Pipelined 32-Bit Advanced RISC Processor for Various D.S.P Applications
Jan 2012
In this paper, the authors propose 32-bit pipelined RISC processor using VLIW architectures. This processor is especially used for both D.S.P applications and general purpose applications. Reduced...
Provided by International Journal of Computer Science and Information Technologies
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White Papers
High Speed and Low Power Dynamic Latched Comparator for PTL Circuit Applications
Jan 2012
Comparators are basic building blocks for designing modern mixed signal systems. Speed and resolution are two important factors which are required for high speed applications. This paper presents...
Provided by International Journal of Computer Science and Information Technologies
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White Papers
Formal Semantics and Analysis of Behavioral AADL Models in Real-Time Maude
Feb 2010
AADL is a standard for modeling embedded systems that is widely used in avionics and other safety-critical applications. However, the AADL standard lacks at present a formal semantics, and this...
Provided by University of Oslo
-
White Papers
Sampling Correlation Sources for Timing Yield Analysis of Sequential Circuits With Clock Networks
Jun 2011
Analyzing timing yield under process variations is difficult because of the presence of correlations. Reconvergent Fan-Out Nodes (RFONs) within combinational subcircuits are a major source of...
Provided by World Scientific Publishing
-
White Papers
CTC: An End-to-End Flow Control Protocol for Multi-Core Systems-on-Chip
May 2009
The authors propose Connection Then Credits (CTC) as a new end-to-end flow control protocol to handle message-dependent deadlocks in Networks-on-Chip (NoC) for multi-core systems-on-chip. CTC is...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Distributed Flit-Buffer Flow Control for Networks-on-Chip
Oct 2008
The combination of flit-buffer flow control methods and latency-insensitive protocols is an effective solution for Networks-on-Chip (NoC). Since they both rely on backpressure, the two techniques...
Provided by Association for Computing Machinery
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White Papers
A Methodology for Constraint-Driven Synthesis of On-Chip Communications
Mar 2009
The authors present a methodology and an optimization framework for the synthesis of on-chip communication through the assembly of components such as interfaces, routers, buses and links, from a...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Time-Division-Multiplexed Arbitration in Silicon Nan photonic Networks-on-Chip for High-Performance Chip Multiprocessors
Oct 2010
As the computational performance of microprocessors continues to grow through the integration of an increasing number of processing cores on a single die, the interconnection network has become...
Provided by Reed Elsevier
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White Papers
Photonic Many-Core Architecture Study
May 2008
Several recent device technology developments have been fundamentally changing the microprocessor architecture design space. These developments include photonic interconnects, feature size...
Provided by University of California
-
White Papers
On-Chip Photonic Communication for High-Performance Multi-Core Processors
Oct 2008
The quest for high-performance and low-power has brought computer architects to design multi-core architectures where an increasing number of parallel processing cores are integrated on a single...
Provided by Columbia University
-
White Papers
A Heterogeneous Parallel System Running Open MPI on a Broadband Network of Embedded Set-Top Devices
May 2010
The authors present a heterogeneous parallel computing system that combines a traditional computer cluster with a broadband network of embedded Set-Top Box (STB) devices. As Multiple Service...
Provided by Association for Computing Machinery
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White Papers
Composing Heterogeneous Reactive Systems
Jul 2008
The authors present a compositional theory of heterogeneous reactive systems. The approach is based on the concept of tags marking the events of the signals of a system. Tags can be used for...
Provided by Association for Computing Machinery
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White Papers
Fault-Tolerant Distributed Deployment of Embedded Control Software
May 2008
Safety-critical feedback-control applications may suffer faults in the controlled plant as well as in the execution platform, i.e., the controller. Control theorists design the control laws to be...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Drop the Phone and Talk to the Physical World: Programming the Internet of Things With Erlang
Mar 2012
The authors present ELIOT, an Erlang-based development framework expressly conceived for heterogeneous and massively decentralized sensing/actuation systems: a vision commonly regarded as the...
Provided by Politecnico di Milano
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White Papers
FPGA Real Time Acceleration for Discrete Wavelet Transform of the 5/3 Filter for JPEG2000 Standard
Mar 2012
In recent years video and image compression have became very required. The availability of powerful software design tools is a fundamental requirement to take advantage of the many advanced and...
Provided by Academy & Industry Research Collaboration Center
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White Papers
Effect of Thread Level Parallelism on the Performance of Optimum Architecture for Embedded Applications
Mar 2012
According to the increasing complexity of network application and internet traffic, network processor as a subset of embedded processors have to process more computation intensive tasks. By...
Provided by Academy & Industry Research Collaboration Center
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White Papers
Leveraging Core Specialization Via OS Scheduling to Improve Performance on Asymmetric Multicore Systems
Apr 2012
Asymmetric Multicore Processors (AMPs) consist of cores with the same ISA (instruction-set architecture), but different micro-architectural features, speed, and power consumption. Because cores...
Provided by Association for Computing Machinery
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White Papers
SAFER: System-Level Architecture for Failure Evasion in Real-Time Applications
Mar 2012
The authors propose a layer called SAFER (System-level Architecture for Failure Evasion in Real-time applications) to incorporate configurable task-level fault-tolerance features such as Hot...
Provided by Carnegie Mellon University
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White Papers
PCOMPATS: Period-Compatible Task Allocation and Splitting on Multi-Core Processors
Jan 2012
Extensive research is underway to build chips with potentially hundreds of cores. In this paper, the authors consider the problem of scheduling periodic real-time tasks on multi-core processors....
Provided by Carnegie Mellon University
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White Papers
Energy-Aware Partitioned Fixed-Priority Scheduling for Chip Multi-Processors
Sep 2011
Energy management is becoming an increasingly important problem in application domains ranging from embedded devices to data centers. In many such systems, multi-core processors are projected as a...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
R-BATCH: Task Partitioning for Fault-Tolerant Multiprocessor Real-Time Systems
Apr 2011
Many emerging embedded real-time applications such as SCADA (Supervisory Control And Data Acquisition), autonomous vehicles and advanced avionics, require a high degree of dependability. Dealing...
Provided by Carnegie Mellon University
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White Papers
Reliability-Driven Energy-Efficient Task Scheduling for Multiprocessor Real-Time Systems
Oct 2011
This paper proposes a reliability-driven task scheduling scheme for multiprocessor real-time embedded systems that optimizes system energy consumption under stochastic fault occurrences. The task...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Transparent, Lightweight Application Execution Replay on Commodity Multiprocessor Operating Systems
Jun 2010
The authors present Scribe, the first system to provide transparent, low-overhead application record-replay and the ability to go live from replayed execution. Scribe introduces new lightweight...
Provided by Association for Computing Machinery
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White Papers
Optimization of N-Queens Solvers on Graphics Processors
Sep 2011
While Graphics Processing Units (GPUs) show high performance for problems with regular structures, they do not perform well for irregular tasks due to the mismatches between irregular problem...
Provided by Springer Science+Business Media
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White Papers
Military Productivity Factors in Large FPGA Designs
Jul 2008
Changes in technology and requirements are leading to FPGAs playing larger roles in defense electronics designs, and consequently are creating both opportunities and risks. The opportunities...
Provided by Altera
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White Papers
DO-254 Support for FPGA Design Flows
Jul 2008
For most defense engineers, the first time they hear about the DO-254 Design Assurance Standard is in a request from their customer beginning with the words "Thou shalt comply with?" This leaves...
Provided by Altera
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White Papers
40-nm FPGAs and the Defense Electronic Design Organization
Jul 2008
With Altera's introduction of 40-nm FPGAs, the design domains of military electronics that can be addressed with Programmable Logic Devices (PLDs) are growing. This growth is a response to...
Provided by Altera
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White Papers
Hardware/Software Co-Verification Using FPGA Platforms
Aug 2008
The problem of hardware and software co-design is as old as systems design and the integration of systems composed of multiple elements. Systems built using electrical and electronic subsystems,...
Provided by Altera
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White Papers
Creating Low-Cost Intelligent Display Modules With an FPGA and Embedded Processor
Sep 2008
LCDs are fast becoming a standard part of the automotive interior. As demand for LCD technology increases, so do methodologies for controlling and creating the displayed graphical content....
Provided by Altera
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White Papers
Applying Graphics to FPGA-Based Solutions
Sep 2008
Like it or not, the Apple iPhone has changed the game. Every device imaginable is getting a revamp with colorful displays and easy-to-use interfaces. Companies are racing frantically to be first...
Provided by Altera
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White Papers
A Flexible Architecture for Fisheye Correction in Automotive Rear-View Cameras
Oct 2008
Fisheye cameras are finding an increasing number of applications in automobile rear-view imaging systems due to their ultra-wide-angle properties and cost-effectiveness. However, while fisheye...
Provided by Altera
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White Papers
Voltage Regulator Selection for FPGAs
Nov 2008
As FPGAs increase in sophistication to provide additional features such as Phase-Locked Loops (PLLs), memory interfaces, and transceiver functionality, the power requirements and designs for FPGAs...
Provided by Altera
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White Papers
FPGAs Enable Energy-Efficient Motor Control in Next-Generation Smart Home Appliances
Nov 2008
Home appliances are at the heart of the modern lifestyle. Consumers want them "Smart," "Green," and, of course, always cheaper. All those diverging requirements have pushed today's home-appliance...
Provided by Altera
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White Papers
40-nm FPGAs: Architecture and Performance Comparison
Dec 2008
FPGA users are constantly looking for ways to differentiate their products in the market place and in doing so they define new systems with new requirements. The new requirements usually are...
Provided by Altera
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White Papers
40-nm FPGA Power Management and Advantages
Dec 2008
The 40-nm process offers clear benefits over prior nodes, including the 65-nm node and the more recent 45-nm node. One of the most attractive benefits is higher integration, which enables...
Provided by Altera
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White Papers
Image-Based Driver Assistance Development Environment
Dec 2008
This white paper describes a development environment for all Driver Assistance (DA) requirements using Altera FPGA and HardCopy ASIC devices. This development environment consists of a development...
Provided by Altera
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White Papers
Leveraging the 40-nm Process Node to Deliver the World's Most Advanced Custom Logic Devices
Feb 2009
Altera's launch of the Stratix IV and HardCopy IV device families in the second quarter of 2008 marked the introduction of the world's first 40-nm FPGAs and the industry's only risk-free path to...
Provided by Altera
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White Papers
Selecting the Ideal FPGA Vendor for Military Programs
Feb 2009
Developing a system design for government projects typically requires a defense contractor to evaluate and make system decisions based on documents such as a Request For Proposal (RFP), Statement...
Provided by Altera
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White Papers
Developing Multipoint Touch Screens and Panels With CPLDs
Feb 2009
When a certain web-enabled multimedia smartphone hit the market in 2007, it transformed the way that consumers expect to interact with their handheld devices. Especially engaging is the fluid...
Provided by Altera
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White Papers
Generating Functionally Equivalent FPGAs and ASICs With a Single Set of RTL and Synthesis/Timing Constraints
Feb 2009
Electronic systems designers use FPGAs for their prototype implementations, taking advantage of the devices' reprogrammability to validate hardware and software. Once the design is ready for...
Provided by Altera
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White Papers
Simplifying Simultaneous Multimode RRH Design
Mar 2009
RRH technology with support for simultaneous operation of multiple air-interface protocols is an emerging end-product requirement. The diverse modulation formats and sampling rates between...
Provided by Altera
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White Papers
Avoiding PCB Design Mistakes in FPGA-Based Systems
Mar 2009
System design using FPGAs is significantly different from the regular ASIC and processor-based system design. This white paper will examine some of the contributing factors, and more importantly,...
Provided by Altera
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White Papers
Automating DSP Simulation and Implementation of Military Sensor Systems
Mar 2009
Military sensor-driven systems normally use FPGAs to interface with the Analog to Digital Converters (ADCs) that digitize sensor inputs. The ADCs operate at rates of up to 3 MSPS, which requires...
Provided by Altera
-
White Papers
Using FPGAs to Render Graphics and Drive LCD Interfaces
Apr 2009
This paper describes the use of FPGAs to add a LCD and GUI display to any embedded system. Unlike fixed processor device implementations, this approach is scalable and can support any display...
Provided by Altera
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White Papers
Generating Panoramic Views by Stitching Multiple Fisheye Images
May 2009
Fisheye cameras are finding an increasing number of applications in automobile imaging systems due to their ultra-wide-angle properties and cost-effectiveness. One such application renders a...
Provided by Altera
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White Papers
FPGA Coprocessing Evolution: Sustained Performance Approaches Peak Performance
Jun 2009
FPGA architecture allows for many algorithm implementations where the sustained performance is much closer to the device's peak performance when compared to quad-core CPUs or GPGPUs. The strong...
Provided by Altera
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White Papers
Protecting the FPGA Design From Common Threats
Jun 2009
The global estimated loss to counterfeiting is expected to exceed U.S.$1.5 trillion in 2009. Counterfeiting impacts all businesses in all markets, from Gucci handbags to computer chips to...
Provided by Altera
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White Papers
Enabling Design Separation for High-Reliability and Information-Assurance Systems
Jun 2009
FPGAs are an ubiquitous part of today's processing technology. Their use has grown from traditional glue logic interfaces of the past to the most advanced information-processing systems used by...
Provided by Altera
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White Papers
Understanding Metastability in FPGAs
Jul 2009
Metastability is a phenomenon that can cause system failure in digital devices, including FPGAs, when a signal is transferred between circuitry in unrelated or asynchronous clock domains. This...
Provided by Altera
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White Papers
Six Ways to Replace a Microcontroller With a CPLD
Jul 2009
This white paper discusses when it is advantageous to use a CPLD instead of a microcontroller, and when a CPLD makes a good companion to a microcontroller. The examples given in this white paper...
Provided by Altera
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White Papers
Reduce Total System Cost in Portable Applications Using Zero-Power CPLDs
Jul 2009
Traditionally, portable system designers have used ASICs and ASSPs to implement memory interfaces, I/O expansion, power-on sequencing, discrete logic functions, display, and other functions in...
Provided by Altera
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White Papers
Implementing a Cost-Effective Human-Machine Interface for Home Appliances
Jul 2009
Traditionally, Human-Machine Interfaces (HMIs) for home appliances have been composed of mechanical devices such as buttons and knobs, coupled with display indicators such as Light-Emitting Diodes...
Provided by Altera
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White Papers
MAX Series Configuration Controller Using Flash Memory
Sep 2009
Configuration bitstream sizes are increasing with the introduction of higher-density FPGAs. This increase requires larger configuration devices to store the data and configure these FPGAs. As an...
Provided by Altera
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White Papers
Adding Hardware Accelerators to Reduce Power in Embedded Systems
Sep 2009
The rule of thumb in embedded system design has been that adding hardware increases power demands. The careful use of hardware accelerators, however, inverts the rule: adding hardware can reduce...
Provided by Altera
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White Papers
Using LEDs as Light-Level Sensors and Emitters
Oct 2009
Modulating LED power based on ambient light level increases battery life, a particularly helpful feature in a device where battery life is measured in days. Using a very simple circuit, Altera's...
Provided by Altera
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White Papers
Leveraging Cost-Optimized FPGAs to Deliver OTN Mapper Solutions
Oct 2009
In telecommunications transport infrastructure, Optical Transport Network (OTN) and Gigabit Ethernet (GbE) protocols are being combined to create Packet-Optical Transport Networks (P-OTNs)....
Provided by Altera
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White Papers
Decrease Total System Costs with Industry's Lowest Cost, Lowest Power FPGAs
Nov 2009
Corporate objectives, such as increasing profits and sales revenue while utilizing R&D efficiently, are putting severe pressure on today's design engineering teams. The resulting system level...
Provided by Altera
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White Papers
Supporting Digital Television Trends With Next-Generation FPGAs
Feb 2010
The proliferation of so many different digital television models-better known as market fragmentation- and differing regional market requirements, combined with the desire to add new features and...
Provided by Altera
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White Papers
Developing Functional Safety Systems With TÜV-Qualified FPGAs
Mar 2010
This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA...
Provided by Altera
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White Papers
Driving Flexibility Into Automotive Electronics Design
Mar 2010
With the dramatic increase in development costs for state-of-the-art process technologies, such as next-generation automotive electronic systems, specialization of traditional microcontrollers no...
Provided by Altera
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White Papers
Extending Transceiver Leadership at 28 nm
May 2010
High-speed serial protocols with increased data rates and expanded capabilities are addressing the demand for more network bandwidth. Efficiently supporting the subsequent increase in system...
Provided by Altera
-
White Papers
Enabling Low-Power EO/IR System Development With FPGAs and Image- and Sensor-Processing IP
Jun 2010
Before embarking on the development of a next-generation Electro-Optical and Infrared (EO/IR) system, it is important to not only understand the power and performance characteristics of the FPGA,...
Provided by Altera
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White Papers
Boosting System Performance With External Memory Solutions
Jun 2010
Over 70% of designs on Altera FPGAs require some type of external memory in the design, but the needs vary depending on the individual application. This white paper addresses all aspects of...
Provided by Altera
-
White Papers
Accelerating DSP Designs With the Total 28-nm DSP Portfolio
Jul 2010
Implementing Digital Signal Processing (DSP) datapaths with different performance, precision, Intellectual Property (IP), and development flows is challenging and labor-intensive. As more and more...
Provided by Altera
-
White Papers
Task Scheduling Algorithm to Reduce the Number of Processors Using Merge Conditions
Feb 2012
Some task scheduling algorithms generate the shortest schedule, when its input DAG satisfies a specified condition. Among those scheduling algorithms, TDS algorithm proposed a DAG condition where...
Provided by Engg Journals Publications
-
White Papers
Digital Logic Embedding Using Single Row
Dec 2011
The authors present a technique to improve embedding capacity of Image using digital logic in this paper. They have applied digital logic operations on two equal halves of an image row to derive...
Provided by Engg Journals Publications
-
White Papers
Energy-Aware Task Partitioning on Heterogeneous Multiprocessor Platforms
Mar 2012
Efficient task partitioning plays a crucial role in achieving high performance at multiprocessor platforms. This paper addresses the problem of energy-aware static partitioning of periodic...
Provided by International Journal of Computer Science Issues
-
White Papers
Design and Implementation of Adder and Subtracter Experiments Using Virtual Intelligent SoftLab
Jan 2012
The scope of this paper includes study and implementation of Full Adder and Subtractor. A full-adder and Subtracter is composed with IC and virtual instruments. Along with the VIS model the...
Provided by International Journal of Computer Science and Telecommunications
-
White Papers
Program Interferometry
Nov 2011
Modern microprocessors have many micro-architectural features. Quantifying the performance impact of one feature such as dynamic branch prediction can be difficult. On one hand, a timing simulator...
Provided by University of Texas
-
White Papers
An Optimized Scaled Neural Branch Predictor
Oct 2011
Conditional branch prediction remains one of the most important enabling technologies for high-performance microprocessors. A small improvement in accuracy can result in a large improvement in...
Provided by University of Texas
-
White Papers
VLSI Implementation of Fast Convolution Based 2-D Discrete Wavelet Transform for High Speed, Area Efficient Image Computing
Mar 2012
A VLSI design approach of a high speed and real-time 2-D Discrete Wavelet Transform computing is being presented in the paper. The proposed architecture, based on new and fast convolution...
Provided by International Journal of Power Control Signal and Computation (IJPCSC)
-
White Papers
Blocking Misbehaving Users In Anonymizying Networks- Embedded Based
Mar 2012
Anonymizing networks such as Tor allow users to access Internet services privately by using a series of routers to hide the client's IP address from the server. The success of such networks,...
Provided by International Journal of Power Control Signal and Computation (IJPCSC)
-
White Papers
Runtime CPU Scheduler Customization Framework for Real Time Operating System
Mar 2012
Most of the embedded systems have real-time requirements about the use of Real-Time Operating Systems able of satisfying the embedded system requirements. So, in embedded application where the...
Provided by International Journal of Computer Technology and Applications
-
White Papers
Design and Implementation of Non Real Time and Real Time Digital Filters for Audio Signal Processing
May 2011
An analog active filter can not provide a very sharp cut-off for both higher and lower frequency component, while a Digital Signal Processor (DSP) using digital filter effectively reduces the...
Provided by Journal of Computing
-
White Papers
Real Time Behavior of Data in Distributed Embedded Systems
Nov 2008
Nowadays, most embedded systems become distributed systems structured as a set of communicating components. Therefore, they display a less deterministic global behavior than centralized systems...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
A Study on the Design of Coaxial Isolator With Filter Circuit
Dec 2011
In this paper, the detailed design of the 1.8 GHz band Y-junction stripline circulator with the low pass filter circuit in the center conductor in order to higher attenuations below value of -30...
Provided by Dongguk University
-
White Papers
Implementation of Area Efficient Memory-Based FIR Digital Filter Using LUT-Multiplier
Mar 2012
Memory based structures are well-suited for many Digital Signal Processing (DSP) applications, which involve multiplication with a fixed set of coefficients. Memory-based structures are more...
Provided by International Journal of Computer Science and Information Technologies
-
White Papers
Integrating Logic Analyzer Functionality Into VHDL Designs
Jan 2012
A combined hardware and software system for the debugging of FPGA designs is designed. It provides a powerful logic analyzer implemented as a fully parameterized VHDL description. The system can...
Provided by International Journal of Computer Science and Information Technologies
-
White Papers
Design and Implementation of Pipelined 32-Bit Advanced RISC Processor for Various D.S.P Applications
Jan 2012
In this paper, the authors propose 32-bit pipelined RISC processor using VLIW architectures. This processor is especially used for both D.S.P applications and general purpose applications. Reduced...
Provided by International Journal of Computer Science and Information Technologies
-
White Papers
High Speed and Low Power Dynamic Latched Comparator for PTL Circuit Applications
Jan 2012
Comparators are basic building blocks for designing modern mixed signal systems. Speed and resolution are two important factors which are required for high speed applications. This paper presents...
Provided by International Journal of Computer Science and Information Technologies
-
White Papers
Formal Semantics and Analysis of Behavioral AADL Models in Real-Time Maude
Feb 2010
AADL is a standard for modeling embedded systems that is widely used in avionics and other safety-critical applications. However, the AADL standard lacks at present a formal semantics, and this...
Provided by University of Oslo
-
White Papers
Sampling Correlation Sources for Timing Yield Analysis of Sequential Circuits With Clock Networks
Jun 2011
Analyzing timing yield under process variations is difficult because of the presence of correlations. Reconvergent Fan-Out Nodes (RFONs) within combinational subcircuits are a major source of...
Provided by World Scientific Publishing
-
White Papers
CTC: An End-to-End Flow Control Protocol for Multi-Core Systems-on-Chip
May 2009
The authors propose Connection Then Credits (CTC) as a new end-to-end flow control protocol to handle message-dependent deadlocks in Networks-on-Chip (NoC) for multi-core systems-on-chip. CTC is...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Distributed Flit-Buffer Flow Control for Networks-on-Chip
Oct 2008
The combination of flit-buffer flow control methods and latency-insensitive protocols is an effective solution for Networks-on-Chip (NoC). Since they both rely on backpressure, the two techniques...
Provided by Association for Computing Machinery
-
White Papers
A Methodology for Constraint-Driven Synthesis of On-Chip Communications
Mar 2009
The authors present a methodology and an optimization framework for the synthesis of on-chip communication through the assembly of components such as interfaces, routers, buses and links, from a...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Time-Division-Multiplexed Arbitration in Silicon Nan photonic Networks-on-Chip for High-Performance Chip Multiprocessors
Oct 2010
As the computational performance of microprocessors continues to grow through the integration of an increasing number of processing cores on a single die, the interconnection network has become...
Provided by Reed Elsevier
-
White Papers
Photonic Many-Core Architecture Study
May 2008
Several recent device technology developments have been fundamentally changing the microprocessor architecture design space. These developments include photonic interconnects, feature size...
Provided by University of California
-
White Papers
On-Chip Photonic Communication for High-Performance Multi-Core Processors
Oct 2008
The quest for high-performance and low-power has brought computer architects to design multi-core architectures where an increasing number of parallel processing cores are integrated on a single...
Provided by Columbia University
-
White Papers
A Heterogeneous Parallel System Running Open MPI on a Broadband Network of Embedded Set-Top Devices
May 2010
The authors present a heterogeneous parallel computing system that combines a traditional computer cluster with a broadband network of embedded Set-Top Box (STB) devices. As Multiple Service...
Provided by Association for Computing Machinery
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White Papers
Composing Heterogeneous Reactive Systems
Jul 2008
The authors present a compositional theory of heterogeneous reactive systems. The approach is based on the concept of tags marking the events of the signals of a system. Tags can be used for...
Provided by Association for Computing Machinery
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White Papers
Fault-Tolerant Distributed Deployment of Embedded Control Software
May 2008
Safety-critical feedback-control applications may suffer faults in the controlled plant as well as in the execution platform, i.e., the controller. Control theorists design the control laws to be...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Drop the Phone and Talk to the Physical World: Programming the Internet of Things With Erlang
Mar 2012
The authors present ELIOT, an Erlang-based development framework expressly conceived for heterogeneous and massively decentralized sensing/actuation systems: a vision commonly regarded as the...
Provided by Politecnico di Milano
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White Papers
FPGA Real Time Acceleration for Discrete Wavelet Transform of the 5/3 Filter for JPEG2000 Standard
Mar 2012
In recent years video and image compression have became very required. The availability of powerful software design tools is a fundamental requirement to take advantage of the many advanced and...
Provided by Academy & Industry Research Collaboration Center
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White Papers
Effect of Thread Level Parallelism on the Performance of Optimum Architecture for Embedded Applications
Mar 2012
According to the increasing complexity of network application and internet traffic, network processor as a subset of embedded processors have to process more computation intensive tasks. By...
Provided by Academy & Industry Research Collaboration Center
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White Papers
Leveraging Core Specialization Via OS Scheduling to Improve Performance on Asymmetric Multicore Systems
Apr 2012
Asymmetric Multicore Processors (AMPs) consist of cores with the same ISA (instruction-set architecture), but different micro-architectural features, speed, and power consumption. Because cores...
Provided by Association for Computing Machinery
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White Papers
SAFER: System-Level Architecture for Failure Evasion in Real-Time Applications
Mar 2012
The authors propose a layer called SAFER (System-level Architecture for Failure Evasion in Real-time applications) to incorporate configurable task-level fault-tolerance features such as Hot...
Provided by Carnegie Mellon University
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White Papers
PCOMPATS: Period-Compatible Task Allocation and Splitting on Multi-Core Processors
Jan 2012
Extensive research is underway to build chips with potentially hundreds of cores. In this paper, the authors consider the problem of scheduling periodic real-time tasks on multi-core processors....
Provided by Carnegie Mellon University
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White Papers
Energy-Aware Partitioned Fixed-Priority Scheduling for Chip Multi-Processors
Sep 2011
Energy management is becoming an increasingly important problem in application domains ranging from embedded devices to data centers. In many such systems, multi-core processors are projected as a...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
R-BATCH: Task Partitioning for Fault-Tolerant Multiprocessor Real-Time Systems
Apr 2011
Many emerging embedded real-time applications such as SCADA (Supervisory Control And Data Acquisition), autonomous vehicles and advanced avionics, require a high degree of dependability. Dealing...
Provided by Carnegie Mellon University
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White Papers
Reliability-Driven Energy-Efficient Task Scheduling for Multiprocessor Real-Time Systems
Oct 2011
This paper proposes a reliability-driven task scheduling scheme for multiprocessor real-time embedded systems that optimizes system energy consumption under stochastic fault occurrences. The task...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Transparent, Lightweight Application Execution Replay on Commodity Multiprocessor Operating Systems
Jun 2010
The authors present Scribe, the first system to provide transparent, low-overhead application record-replay and the ability to go live from replayed execution. Scribe introduces new lightweight...
Provided by Association for Computing Machinery
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White Papers
Optimization of N-Queens Solvers on Graphics Processors
Sep 2011
While Graphics Processing Units (GPUs) show high performance for problems with regular structures, they do not perform well for irregular tasks due to the mismatches between irregular problem...
Provided by Springer Science+Business Media
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White Papers
Design and Optimization of Full Comparator Based on Quantum-Dot Cellular Automata
Apr 2012
Quantum-dot Cellular Automata (QCA) is one of the few alternative computing platforms that has the potential to be a promising technology because of higher speed, smaller size, and lower power...
Provided by ETRI Journal
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White Papers
Energy-Efficient Hardware Data Prefetching
Feb 2011
Extensive research has been done in prefetching techniques that hide memory latency in microprocessors leading to performance improvements. However, the energy aspect of prefetching is relatively...
Provided by Institute of Electrical & Electronic Engineers
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