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asics - chip sets
(387 results)-
Whitepapers
Inside Intel IT on Cloud Computing and Security
Jan 2012
Certainly no one expects that a company like Intel doesn't have issues when it comes to computing in the cloud, they do by the way. The real question is, how do they handle them, what are Intel...
Provided by Intel Corporation
-
White Papers
New Intel® Atom™ Dev SDK brings enhancements & component integration
Jun 2010
The Intel® Atom™ Developer Program has just released Beta 3 of its Windows SDK. With this new release, there are a number of enhancements to assist with application development, and it offers a...
Provided by Intel
-
White Papers
Windows 7 - Mobile Broadband Certification for Existing Chipsets
Mar 2009
This paper provides information about Windows 7 support for Mobile Broadband. It provides guidelines for hardware manufacturers, original equipment manufacturers, and mobile network operators on...
Provided by Microsoft
-
White Papers
Power Improvements on 2008 Desktop Platforms
Oct 2008
This paper presents platform- and silicon component power data that demonstrate advances in desktop platform power management enabled on 2008 platforms, built with the Intel Q45 Express Chipset,...
Provided by Intel
-
White Papers
Consolidating DSS Workloads on Dell PowerEdge 11G Servers Using Oracle 11g Database Replay
Apr 2009
Any server consolidation project must be preceded by a well-planned effort to predict the energy consumption and performance capacity of the new platform as compared to the legacy environment....
Provided by Dell
-
White Papers
Performance Report PRIMERGY RX300 S4
Dec 2007
The PRIMERGY RX300 S4 is a space-saving dual socket rack server which takes up just 2 height units and replaces the PRIMERGY RX300 S3. It has an Intel 5000P chipset, two Intel Dual-Core or...
Provided by Fujitsu Siemens
-
White Papers
Windows ACPI Emulated Devices Table
Apr 2009
Modern PC platforms often use devices that have known errata. In this case, the Windows family of operating systems may include mechanisms to work around these known errata whenever possible. Two...
Provided by Microsoft
-
White Papers
Performance Advantage of Dell PowerEdge R900 over HP DL585 Running Microsoft Hyper-V
Sep 2008
Information Technology organizations are finding that combining today's industry standard servers based on multi-core processors with server virtualization can create highly efficient solutions. A...
Provided by Dell
-
Tools & Templates
Intel® Atom™ Developer Program's Million Dollar Developer Fund
Mar 2010
Netbooks' mobility and smaller screen sizes demand applications that are optimized for a mobile, on-the-go audience. The Intel Atom Developer Program Million Dollar Development Fund helps...
Provided by Intel
-
White Papers
Optimizing Power Distribution for High-Density Computing
Apr 2010
Choosing the right power distribution units for today and preparing for the future Fueled by the rapid rise of technologies such as virtualization and blade servers, computing densities in...
Provided by Eaton
-
Whitepapers
An Area Efficient 32-Bit Carry-Select Adder for Low Power Applications
Jul 2012
CSLA is used in many computational systems to alleviate the problem of carry propagation delay by independently generating multiple carries and then select a carry to generate the sum. However,...
Provided by Interscience Open Access Journals
-
Whitepapers
Edge-Triggered Pulsed Sequential Elements With SoC Applications
Jul 2012
The System-On-Chip (SoC) design is integrating hundreds of millions of transistors on one chip, whereas packaging and cooling only have a limited ability to remove the excess heat. In this paper,...
Provided by Interscience Open Access Journals
-
Whitepapers
Calibration of SDR Circuit Imperfections
Oct 2008
Software Defined Radio (SDR) transceivers comprising a single highly reconfigurable circuit have proven to enable multi-mode multi-band operation at low-cost. However, distortion induced by...
Provided by Institute of Electrical & Electronic Engineers
-
White Papers
SCOC3: A Space Computer on a Chip - An Example of Successful Development of a Highly Integrated Innovative ASIC
Feb 2010
This paper presents the definition of an integrated processor core ASIC named SCOC3 which is designed for space computers. It also presents the validation method that has led to a successful ASIC...
Provided by Economic Development Association of Alabama
-
White Papers
Achieving One TeraFLOPS With 28-nm FPGAs
Sep 2010
Due to recent technological developments, high-performance floating-point signal processing can, for the first time, be easily achieved using FPGAs. To date, virtually all FPGA-based signal...
Provided by Altera
-
White Papers
Fulfilling Technology Needs for 40G-100G Network-Centric Operations and Warfare
Sep 2010
The development and deployment of Network-Centric Operations and Warfare (NCOW) to integrate and connect the military's many separate networks relies on high-speed packet transport and optical...
Provided by Altera
-
White Papers
Board Design Guidelines for LVDS Systems
Sep 2010
LVDS is a high-speed, low-voltage, low-power, and low-noise general-purpose I/O interface standard. The low-voltage swing and differential current mode outputs significantly reduce Electromagnetic...
Provided by Altera
-
White Papers
Implementing FIR Filters and FFTs With 28-nm Variable-Precision DSP Architecture
Sep 2010
Across a range of applications, the two most common functions implemented in FPGA-based high-performance signal processing are Finite Impulse Response (FIR) filters and fast Fourier transforms...
Provided by Altera
-
White Papers
Guaranteeing Silicon Performance With FPGA Timing Models
Aug 2010
How can a designer accurately predict the time delays of a fully customizable integrated circuit? The answer to this question is "Not very easily." There are many factors that limit and increase...
Provided by Altera
-
White Papers
Enhancing Robust SEU Mitigation With 28-nm FPGAs
Jul 2010
Systems designed with FPGAs benefit from significant improvements over ASICS, such as rapid-process technology scaling and design innovation, which permit the use of FPGAs in high-availability,...
Provided by Altera
-
White Papers
Medical Imaging Implementation Using FPGAs
Jul 2010
Earlier prediction and treatment are driving the fusion of modalities such as Positron Emission Tomography (PET)/Computerized Tomography (CT) and X-ray/CT equipment. The higher image resolutions...
Provided by Altera
-
White Papers
Addressing 100-GbE Line-Card Design Challenges on 28-nm FPGAs
Jul 2010
As various standard bodies finalize their 100G standards for transport, Ethernet, and optical interfaces, FPGAs play a vital role for early adopters of technology who want to design 100G...
Provided by Altera
-
White Papers
Increasing Design Functionality With Partial and Dynamic Reconfiguration in 28-nm FPGAs
Jul 2010
The density of FPGAs has grown with each process node shrink. Compared to previous generations of FPGAs, the extra density, coupled with features such as reconfiguration, enables designers to add...
Provided by Altera
-
White Papers
Innovating With a Full Spectrum of 40-nm FPGAs and ASICs With Transceivers
Jul 2010
Increasing bandwidth requirements for broadband services are driving silicon vendors to use more and more high-speed serial transceivers. Therefore, next-generation applications feature a wide...
Provided by Altera
-
White Papers
Integrating 100-GbE Switching Solutions on 28-nm FPGAs
Jul 2010
With high-speed 100-GbE communication network standards converging, switching functions play a key role in the smooth functioning of the Internet. The aggregated network traffic doubles every six...
Provided by Altera
-
White Papers
Understanding 40-nm FPGA Solutions for SATA/SAS
Jul 2010
Serial ATA (SATA) and Serial Attached SCSI (SAS) are computer bus standards that have the primary function of transferring data (directly or otherwise) between the motherboard and mass storage...
Provided by Altera
-
White Papers
Accelerating DSP Designs With the Total 28-nm DSP Portfolio
Jul 2010
Implementing Digital Signal Processing (DSP) datapaths with different performance, precision, Intellectual Property (IP), and development flows is challenging and labor-intensive. As more and more...
Provided by Altera
-
White Papers
Building an IP Surveillance Camera System With a Low-Cost FPGA
Jun 2010
In the video surveillance marketplace, the need for higher quality video, higher resolution, and more flexibility and features is driving the change from analog to digital cameras. By definition,...
Provided by Altera
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White Papers
Boosting System Performance With External Memory Solutions
Jun 2010
Over 70% of designs on Altera FPGAs require some type of external memory in the design, but the needs vary depending on the individual application. This white paper addresses all aspects of...
Provided by Altera
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White Papers
Enabling Low-Power EO/IR System Development With FPGAs and Image- and Sensor-Processing IP
Jun 2010
Before embarking on the development of a next-generation Electro-Optical and Infrared (EO/IR) system, it is important to not only understand the power and performance characteristics of the FPGA,...
Provided by Altera
-
White Papers
Enabling High-Precision DSP Applications With the FPGA Industry's First Variable-Precision Architecture
May 2010
The silicon Digital Signal Processing (DSP) architecture of the FPGA can make a big difference when implementing complex signal-processing algorithms. Altera's Stratix V FPGAs, with the...
Provided by Altera
-
White Papers
Extending Transceiver Leadership at 28 nm
May 2010
High-speed serial protocols with increased data rates and expanded capabilities are addressing the demand for more network bandwidth. Efficiently supporting the subsequent increase in system...
Provided by Altera
-
White Papers
Enabling Improved Image Format Conversion With FPGAs
Apr 2010
Broadcast infrastructure systems - such as servers, switchers, head-end encoders, and specialty studio displays - support a multitude of input image formats, and commonly require images to be...
Provided by Altera
-
White Papers
Driving Flexibility Into Automotive Electronics Design
Mar 2010
With the dramatic increase in development costs for state-of-the-art process technologies, such as next-generation automotive electronic systems, specialization of traditional microcontrollers no...
Provided by Altera
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White Papers
Developing Functional Safety Systems With TÜV-Qualified FPGAs
Mar 2010
This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA...
Provided by Altera
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White Papers
Using 10-Gbps Transceivers in 40G/100G Applications
Feb 2010
This white paper identifies the key drivers behind the migration to 100G interfaces, and shows how to leverage the unique ability of FPGAs to implement this high-speed interface. The emerging...
Provided by Altera
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White Papers
Supporting Digital Television Trends With Next-Generation FPGAs
Feb 2010
The proliferation of so many different digital television models-better known as market fragmentation- and differing regional market requirements, combined with the desire to add new features and...
Provided by Altera
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White Papers
Decrease Total System Costs with Industry's Lowest Cost, Lowest Power FPGAs
Nov 2009
Corporate objectives, such as increasing profits and sales revenue while utilizing R&D efficiently, are putting severe pressure on today's design engineering teams. The resulting system level...
Provided by Altera
-
White Papers
Taking Advantage of Advances in FPGA Floating-Point IP Cores
Oct 2009
Recently available FPGA design tools and IP provide a substantial reduction in computational resources, as well as greatly easing the implementation effort in a floating-point datapath. Moreover,...
Provided by Altera
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White Papers
High-Definition Video Deinterlacing Using FPGAs
Oct 2009
Deinterlacing was developed to address a legacy problem: the interlaced video that was required by old analog televisions must be converted to be shown on today's digital televisions. An...
Provided by Altera
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Whitepapers
Efficient DPA Attacks on AES Hardware Implementations
Feb 2008
In this paper, the authors present an effective way to enhance power analysis attacks on AES hardware implementations. The proposed attack adopts hamming difference of intermediate results as...
Provided by Scientific Research
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Whitepapers
Folded Architecture of Scheduler for Area Optimization in On-Chip Switch Fabric
Mar 2011
As the feature sizes of the manufacturing processes are constantly shrinking, the possibility and demand for more functionality on a single chip goes up. This can lead to many problems e.g. as the...
Provided by Science and Development Network (SciDev.Net)
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Whitepapers
Three Dimensional-Chips
Oct 2012
This paper illustrates the performance advantages of 3D integrated circuits with two specific examples, namely 3D-FPGA and 3D-SRAM. Three-dimensional Chip (3D IC, 3D-IC, or 3-D IC) is a chip in...
Provided by IOSR Journal of Engineering
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Whitepapers
BPSK Transmitter Design Using FPGA With DAC and Pulse Shaping Filter to Minimize Inter-Symbol Interference(ISI)
Feb 2013
In contrast to the sophisticated implementation of Binary Phase Shift Keying (BPSK) transmitter using Application Specific Integrated Circuit (ASIC), mixer, and Local Oscillator(LO) for carrier...
Provided by IOSR Journal of Engineering
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Whitepapers
Partial Matching Mixed Mode BIST Design for Test Data Reduction
Mar 2012
A mixed-mode Built-In Self-Test (BIST) approach that deploys two new techniques is presented in this paper. Partial pattern matching allows the reduction of the number of patterns used for...
Provided by International Journal of Communications and Engineering
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Whitepapers
Design and Verification of Performance of 32 Bit High Speed Truncation-Error -Tolerant Adder
Aug 2012
In this paper, the authors have proposed an architecture for high speed Truncation Adder Algorithm. In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. By...
Provided by The World
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Whitepapers
Efficient Weighted Pattern Generation Technique With Low Hardware Overhead
Jan 2013
Weighted pseudorandom Built-In Self Test (BIST) schemes have been utilized in order to drive down the number of vectors to achieve complete fault coverage in BIST applications. Weighted sets...
Provided by The World
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Whitepapers
VHDL Simulation of Reset Automatic Block, 64bit Latch Block, and Test Complete Blocks ForPD Detection Circuit System Using FPGA
Mar 2012
This paper is purely a model to determine the design circuit to implement Partial Discharge (PD) detection in FPGA technology. The research shall involve ISE Simulator version 10.1i (Xilinx) and...
Provided by International Journal of Communications and Engineering
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Whitepapers
FPGA Realization of Open/Short Test on IC
Feb 2008
IC (Integrated Circuitry) testing requires the very advanced and sophisticated Advance Test Equipment (ATE) that costs multimillion USD. The cost of IC testing is increasing yearly and it will...
Provided by NORTH ATLANTIC UNIVERSITY UNION
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Whitepapers
Design and ASIC Implementation of Root Raised Cosine Filter
Jun 2009
Raised cosine filter is a FIR filter that can be used to counter many problems of communication such as the Inter symbol interference. The rectangular pulse occupies a large bandwidth so an...
Provided by EuroJournals
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Whitepapers
ASIC Implementation of Modified Faster Carry Save Adder
Nov 2010
Digital adders are the core block of DSP processors. The final Carry Propagation Adder (CPA) structure of many adders constitutes high carry propagation delay and this delay reduces the overall...
Provided by EuroJournals
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Whitepapers
Simulation Based Multifunctional MOS Device by Externally Controlled Gate Width
Aug 2011
The world's demand for high-speed devices and equipments are growing very drastically. Every individual researcher in all country is marching towards, to achieve it .The role of Design Engineer...
Provided by EuroJournals
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Whitepapers
ASIC Implementation of Scalable Encryption Algorithm Using Efficient Modular Adders
Mar 2012
Resource constrained encryption does not have an extensive history in symmetric cryptography. Examples of recent lightweight block ciphers are HIGHT and PRESENT. However, both of them do not...
Provided by EuroJournals
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Whitepapers
ASIC and FPGA Implementation Strategies for Model Predictive Control
Jun 2009
Model Predictive Control (MPC) techniques have recently enjoyed an upsurge of interest within the automatic control community, due to their ability to handle non-linear systems and constraints on...
Provided by University of New York in Prague
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Whitepapers
FPGA-Based Verification Methodology of SOC-Type CMOS Image Signal Processor
Oct 2009
This paper describes a FPGA-based verification methodology for the Image Signal Processor (ISP) of System-on-Chip (SoC) type CMOS image sensor. To make a verification environment, the complete...
Provided by Institute of Electrical & Electronic Engineers
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Whitepapers
Design and Analysis of Finite Impulse Response Using G Ate Diffusion Input (GDI) Circuits
Jul 2011
Integrated Circuits technology advancements have consistently migrated to smaller feature sizes over the last four decades years, forcing more functional circuits to be placed on each chip. The...
Provided by Dynamic Publishers
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Whitepapers
Repair Analysis for Embedded Memories Using Block-Based Redundancy Architecture
Jul 2012
Capacity and density of embedded memories have rapidly increased therefore they have higher probability of faults. As a result, yield of system-on-a-chip designs with embedded memories drops....
Provided by International Association of Engineers
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Whitepapers
Flip-Flop Circuit Families: Comparison of Layout and Topology for Low Power VLSI Circuits
Nov 2011
The pertinent choice of flip-flop topologies is an essential importance in the design of VLSI integrated circuits for high speed and high performance CMOS circuits. Understanding the suitability...
Provided by International Journal of Engineering Research and Applications (IJERA)
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Whitepapers
Module Based and Difference Based Implementation of Partial Reconfiguration on FPGA: A Review
Nov 2011
Dynamically adaptable computing systems are promising research area at developing systems which can adapt to changes in their environment while executing. The premisses for such systems are...
Provided by International Journal of Engineering Research and Applications (IJERA)
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Whitepapers
Design and Synthesis of a Field Programmable CRC Circuit Architecture
Jul 2011
The design and implementation of a programmable Cyclic Redundancy Check (CRC) computation circuit architecture, suitable for deployment in network related System-on-Chips (SoCs) is presented. The...
Provided by International Journal of Engineering Research and Applications (IJERA)
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Whitepapers
Digital Clock Frequency Multiplier Using Floating Point Arithmetic
Aug 2012
A digital clock frequency multiplier using floating point arithmetic, which generates the output clock with zero frequency error has been presented. The circuit has an unbounded multiplication...
Provided by International Journal of Engineering Research and Development (IJERD)
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Whitepapers
SysGen Architecture for Visual Information Hiding Framework
Mar 2012
The development time and cost for DSP solution have been improved significantly due to proliferation of rapid prototyping tools such as MATLAB-Simulink and Xilinx System Generator (SysGen). The...
Provided by International Journal of Emerging Technology and Advanced Engineering (IJETAE)
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Whitepapers
Comparison of Self-Timed Ring and Inverter Ring Oscillators as Entropy Sources in FPGAs
Feb 2012
Many True Random Numbers Generators (TRNG) use jittery clocks generated in ring oscillators as a source of entropy. This is especially the case in Field Programmable Gate Arrays (FPGA), where...
Provided by INRIA
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Whitepapers
Design and Implementation of Viterbi Encoder and Decoder Using FPGA
Jun 2012
In this paper, the authors present an implementation of the Viterbi algorithm using the Hardware Description Language and Implemented on FPGA. They begin with a description of the algorithm....
Provided by International Journal of Engineering and Advanced Technology (IJEAT)
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Whitepapers
Toward a Circuit Theory of Communication
Jul 2010
Electromagnetic field theory provides the physics of radio communications, while information theory approaches the problem from a purely mathematical point of view. While there is a law of...
Provided by Institute of Electrical & Electronic Engineers
-
Whitepapers
A Multiport Theory of Communications
Jan 2010
Electro-magnetics provides the ground for a physical theory of communications, while information theory and signal theory approach the problem from a purely mathematical point of view....
Provided by Institute of Electrical & Electronic Engineers
-
Whitepapers
Effect of Electrostatic Discharge on Digital and Analog Circuits
Aug 2012
A comparative study of the effects of ElectroStatic Discharge (ESD) on digital and analog circuits is carried out. Direct and Indirect discharge is performed on the circuit having both analog and...
Provided by IOSR Journal of Engineering
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Whitepapers
Multiplierless FIR Filter Implementation on FPGA
May 2012
Area complexity in the algorithm of Finite Impulse Response (FIR) filter is mainly caused by multipliers. Among the multiplier-less techniques of FIR filter, Distributed Arithmetic is most...
Provided by International Journal of Information and Electronics Engineering
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Whitepapers
Fast and Compact ASIC Implementation of SFlash New Signature Scheme
Oct 2009
The idea of using multivariate polynomials as public keys has attracted several cryptographers, SFlash signature scheme is a variant of the Matsumoto and Imai multivariate public Key cryptosystem...
Provided by Science and Development Network (SciDev.Net)
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Whitepapers
FPGA Based Area and Throughput Implementation of JH and BLAKE Hash Function
Apr 2012
Implementation of area and throughput of the main building block (compression function) for two SHA-3 candidates BLAKE and JH hash function. The National Institute of Standards and Technology...
Provided by IJCTT-International Journal of Computer Trends and Technology
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Whitepapers
Implementation of SOBEL Edge Detection on FPGA
Jun 2012
The image processing algorithms has been limited to software implementation which is slower due to the limited processor speed. So, a dedicated processor for edge detection is required which was...
Provided by IJCTT-International Journal of Computer Trends and Technology
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Whitepapers
A New Reduced Clock Power Flip-Flop for Future SOC Applications
Aug 2012
In this paper a novel technique is proposed based on the comparison between Conventional Conditional Data Mapping Flip-flop and Clock Pair Shared D Flip Flop (CPSFF) here the authors are checking...
Provided by IJCTT-International Journal of Computer Trends and Technology
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Whitepapers
FPGA and ASIC Implementation of Vedic Multiplier
Jul 2012
The ever increasing demand in enhancing the ability of processors to handle the complex and challenging processes has resulted in the integration of a number of processor cores into one chip....
Provided by International forum of researchers Students and Academician
-
Whitepapers
Calibration of SDR Circuit Imperfections
Oct 2008
Software Defined Radio (SDR) transceivers comprising a single highly reconfigurable circuit have proven to enable multi-mode multi-band operation at low-cost. However, distortion induced by...
Provided by Institute of Electrical & Electronic Engineers
-
Whitepapers
Edge-Triggered Pulsed Sequential Elements With SoC Applications
Jul 2012
The System-On-Chip (SoC) design is integrating hundreds of millions of transistors on one chip, whereas packaging and cooling only have a limited ability to remove the excess heat. In this paper,...
Provided by Interscience Open Access Journals
-
Whitepapers
An Area Efficient 32-Bit Carry-Select Adder for Low Power Applications
Jul 2012
CSLA is used in many computational systems to alleviate the problem of carry propagation delay by independently generating multiple carries and then select a carry to generate the sum. However,...
Provided by Interscience Open Access Journals
-
Whitepapers
The IP Soft-Core Design pf ADC and PLD Verification
Jul 2010
Analog to Digital Converters (ADC) are important components of the Input /Output system in a Large-Scale Integrated Circuit, And the applied value is very high. Such as wireless communications,...
Provided by Academy Publisher
-
Whitepapers
Reversible Circuit Optimization Using PSO Algorithm
Jun 2012
Reversible Circuits Synthesis and optimization is one of the main terms dealt with in this paper. The synthesis and optimization of circuits using PSO algorithm is investigated in this paper. In...
Provided by Islamic Azad University
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Whitepapers
Augmenting Computer Architecture Classroom Experience With FPGAs Based Learning
Aug 2012
Computer architecture is often taught by using software to design and simulate hardware modules and then using individual components to implement them. The authors' aim of this paper is to share...
Provided by International Journal of Computer Theory and Engineering (IJCTE)
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Whitepapers
Survey on FPGA Routing Techniques
Jul 2012
Field Programmable Gate Array (FPGA), a programmable integrated circuit, has gained great popularity in the circuit design. Routing is an important part of FPGA design step which determines the...
Provided by Engg Journals Publications
-
White Papers
Windows 7 - Mobile Broadband Certification for Existing Chipsets
Mar 2009
This paper provides information about Windows 7 support for Mobile Broadband. It provides guidelines for hardware manufacturers, original equipment manufacturers, and mobile network operators on...
Provided by Microsoft
-
White Papers
Power Improvements on 2008 Desktop Platforms
Oct 2008
This paper presents platform- and silicon component power data that demonstrate advances in desktop platform power management enabled on 2008 platforms, built with the Intel Q45 Express Chipset,...
Provided by Intel
-
White Papers
Consolidating DSS Workloads on Dell PowerEdge 11G Servers Using Oracle 11g Database Replay
Apr 2009
Any server consolidation project must be preceded by a well-planned effort to predict the energy consumption and performance capacity of the new platform as compared to the legacy environment....
Provided by Dell
-
White Papers
Performance Report PRIMERGY RX300 S4
Dec 2007
The PRIMERGY RX300 S4 is a space-saving dual socket rack server which takes up just 2 height units and replaces the PRIMERGY RX300 S3. It has an Intel 5000P chipset, two Intel Dual-Core or...
Provided by Fujitsu Siemens
-
White Papers
Windows ACPI Emulated Devices Table
Apr 2009
Modern PC platforms often use devices that have known errata. In this case, the Windows family of operating systems may include mechanisms to work around these known errata whenever possible. Two...
Provided by Microsoft
-
White Papers
Performance Advantage of Dell PowerEdge R900 over HP DL585 Running Microsoft Hyper-V
Sep 2008
Information Technology organizations are finding that combining today's industry standard servers based on multi-core processors with server virtualization can create highly efficient solutions. A...
Provided by Dell
-
Tools & Templates
Intel® Atom™ Developer Program's Million Dollar Developer Fund
Mar 2010
Netbooks' mobility and smaller screen sizes demand applications that are optimized for a mobile, on-the-go audience. The Intel Atom Developer Program Million Dollar Development Fund helps...
Provided by Intel
-
White Papers
Optimizing Power Distribution for High-Density Computing
Apr 2010
Choosing the right power distribution units for today and preparing for the future Fueled by the rapid rise of technologies such as virtualization and blade servers, computing densities in...
Provided by Eaton
-
White Papers
New Intel® Atom™ Dev SDK brings enhancements & component integration
Jun 2010
The Intel® Atom™ Developer Program has just released Beta 3 of its Windows SDK. With this new release, there are a number of enhancements to assist with application development, and it offers a...
Provided by Intel
-
Whitepapers
An Area Efficient 32-Bit Carry-Select Adder for Low Power Applications
Jul 2012
CSLA is used in many computational systems to alleviate the problem of carry propagation delay by independently generating multiple carries and then select a carry to generate the sum. However,...
Provided by Interscience Open Access Journals
-
Whitepapers
Edge-Triggered Pulsed Sequential Elements With SoC Applications
Jul 2012
The System-On-Chip (SoC) design is integrating hundreds of millions of transistors on one chip, whereas packaging and cooling only have a limited ability to remove the excess heat. In this paper,...
Provided by Interscience Open Access Journals
-
Whitepapers
Calibration of SDR Circuit Imperfections
Oct 2008
Software Defined Radio (SDR) transceivers comprising a single highly reconfigurable circuit have proven to enable multi-mode multi-band operation at low-cost. However, distortion induced by...
Provided by Institute of Electrical & Electronic Engineers
-
White Papers
SCOC3: A Space Computer on a Chip - An Example of Successful Development of a Highly Integrated Innovative ASIC
Feb 2010
This paper presents the definition of an integrated processor core ASIC named SCOC3 which is designed for space computers. It also presents the validation method that has led to a successful ASIC...
Provided by Economic Development Association of Alabama
-
White Papers
Achieving One TeraFLOPS With 28-nm FPGAs
Sep 2010
Due to recent technological developments, high-performance floating-point signal processing can, for the first time, be easily achieved using FPGAs. To date, virtually all FPGA-based signal...
Provided by Altera
-
White Papers
Fulfilling Technology Needs for 40G-100G Network-Centric Operations and Warfare
Sep 2010
The development and deployment of Network-Centric Operations and Warfare (NCOW) to integrate and connect the military's many separate networks relies on high-speed packet transport and optical...
Provided by Altera
-
White Papers
Board Design Guidelines for LVDS Systems
Sep 2010
LVDS is a high-speed, low-voltage, low-power, and low-noise general-purpose I/O interface standard. The low-voltage swing and differential current mode outputs significantly reduce Electromagnetic...
Provided by Altera
-
White Papers
Implementing FIR Filters and FFTs With 28-nm Variable-Precision DSP Architecture
Sep 2010
Across a range of applications, the two most common functions implemented in FPGA-based high-performance signal processing are Finite Impulse Response (FIR) filters and fast Fourier transforms...
Provided by Altera
-
White Papers
Guaranteeing Silicon Performance With FPGA Timing Models
Aug 2010
How can a designer accurately predict the time delays of a fully customizable integrated circuit? The answer to this question is "Not very easily." There are many factors that limit and increase...
Provided by Altera
-
White Papers
Enhancing Robust SEU Mitigation With 28-nm FPGAs
Jul 2010
Systems designed with FPGAs benefit from significant improvements over ASICS, such as rapid-process technology scaling and design innovation, which permit the use of FPGAs in high-availability,...
Provided by Altera
-
White Papers
Medical Imaging Implementation Using FPGAs
Jul 2010
Earlier prediction and treatment are driving the fusion of modalities such as Positron Emission Tomography (PET)/Computerized Tomography (CT) and X-ray/CT equipment. The higher image resolutions...
Provided by Altera
-
White Papers
Addressing 100-GbE Line-Card Design Challenges on 28-nm FPGAs
Jul 2010
As various standard bodies finalize their 100G standards for transport, Ethernet, and optical interfaces, FPGAs play a vital role for early adopters of technology who want to design 100G...
Provided by Altera
-
White Papers
Increasing Design Functionality With Partial and Dynamic Reconfiguration in 28-nm FPGAs
Jul 2010
The density of FPGAs has grown with each process node shrink. Compared to previous generations of FPGAs, the extra density, coupled with features such as reconfiguration, enables designers to add...
Provided by Altera
-
White Papers
Innovating With a Full Spectrum of 40-nm FPGAs and ASICs With Transceivers
Jul 2010
Increasing bandwidth requirements for broadband services are driving silicon vendors to use more and more high-speed serial transceivers. Therefore, next-generation applications feature a wide...
Provided by Altera
-
White Papers
Integrating 100-GbE Switching Solutions on 28-nm FPGAs
Jul 2010
With high-speed 100-GbE communication network standards converging, switching functions play a key role in the smooth functioning of the Internet. The aggregated network traffic doubles every six...
Provided by Altera
-
White Papers
Understanding 40-nm FPGA Solutions for SATA/SAS
Jul 2010
Serial ATA (SATA) and Serial Attached SCSI (SAS) are computer bus standards that have the primary function of transferring data (directly or otherwise) between the motherboard and mass storage...
Provided by Altera
-
White Papers
Accelerating DSP Designs With the Total 28-nm DSP Portfolio
Jul 2010
Implementing Digital Signal Processing (DSP) datapaths with different performance, precision, Intellectual Property (IP), and development flows is challenging and labor-intensive. As more and more...
Provided by Altera
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White Papers
Building an IP Surveillance Camera System With a Low-Cost FPGA
Jun 2010
In the video surveillance marketplace, the need for higher quality video, higher resolution, and more flexibility and features is driving the change from analog to digital cameras. By definition,...
Provided by Altera
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White Papers
Boosting System Performance With External Memory Solutions
Jun 2010
Over 70% of designs on Altera FPGAs require some type of external memory in the design, but the needs vary depending on the individual application. This white paper addresses all aspects of...
Provided by Altera
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White Papers
Enabling Low-Power EO/IR System Development With FPGAs and Image- and Sensor-Processing IP
Jun 2010
Before embarking on the development of a next-generation Electro-Optical and Infrared (EO/IR) system, it is important to not only understand the power and performance characteristics of the FPGA,...
Provided by Altera
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White Papers
Enabling High-Precision DSP Applications With the FPGA Industry's First Variable-Precision Architecture
May 2010
The silicon Digital Signal Processing (DSP) architecture of the FPGA can make a big difference when implementing complex signal-processing algorithms. Altera's Stratix V FPGAs, with the...
Provided by Altera
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White Papers
Extending Transceiver Leadership at 28 nm
May 2010
High-speed serial protocols with increased data rates and expanded capabilities are addressing the demand for more network bandwidth. Efficiently supporting the subsequent increase in system...
Provided by Altera
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White Papers
Enabling Improved Image Format Conversion With FPGAs
Apr 2010
Broadcast infrastructure systems - such as servers, switchers, head-end encoders, and specialty studio displays - support a multitude of input image formats, and commonly require images to be...
Provided by Altera
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White Papers
Driving Flexibility Into Automotive Electronics Design
Mar 2010
With the dramatic increase in development costs for state-of-the-art process technologies, such as next-generation automotive electronic systems, specialization of traditional microcontrollers no...
Provided by Altera
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White Papers
Developing Functional Safety Systems With TÜV-Qualified FPGAs
Mar 2010
This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA...
Provided by Altera
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White Papers
Using 10-Gbps Transceivers in 40G/100G Applications
Feb 2010
This white paper identifies the key drivers behind the migration to 100G interfaces, and shows how to leverage the unique ability of FPGAs to implement this high-speed interface. The emerging...
Provided by Altera
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White Papers
Supporting Digital Television Trends With Next-Generation FPGAs
Feb 2010
The proliferation of so many different digital television models-better known as market fragmentation- and differing regional market requirements, combined with the desire to add new features and...
Provided by Altera
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White Papers
Decrease Total System Costs with Industry's Lowest Cost, Lowest Power FPGAs
Nov 2009
Corporate objectives, such as increasing profits and sales revenue while utilizing R&D efficiently, are putting severe pressure on today's design engineering teams. The resulting system level...
Provided by Altera
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White Papers
Taking Advantage of Advances in FPGA Floating-Point IP Cores
Oct 2009
Recently available FPGA design tools and IP provide a substantial reduction in computational resources, as well as greatly easing the implementation effort in a floating-point datapath. Moreover,...
Provided by Altera
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White Papers
High-Definition Video Deinterlacing Using FPGAs
Oct 2009
Deinterlacing was developed to address a legacy problem: the interlaced video that was required by old analog televisions must be converted to be shown on today's digital televisions. An...
Provided by Altera
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White Papers
Leveraging Cost-Optimized FPGAs to Deliver OTN Mapper Solutions
Oct 2009
In telecommunications transport infrastructure, Optical Transport Network (OTN) and Gigabit Ethernet (GbE) protocols are being combined to create Packet-Optical Transport Networks (P-OTNs)....
Provided by Altera
