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asics - chip sets
(387 results)-
White Papers
Developing MSAN Equipment Using Low-Cost FPGAs
Jan 2008
This paper looks at the trends in the Multi-Service Access Node (MSAN) equipment market that are forcing developers to re-examine the architectures they have used in the past, as well as driving...
Provided by Altera
-
White Papers
Electronic Warfare Design With PLDs and High-Speed Transceivers
Dec 2007
Electronic warfare has become part of the strategic landscape for all warfighters on the ground, at sea, and in the air. Threats change quickly, so fast characterization of the electromagnetic...
Provided by Altera
-
White Papers
Basic Principles of Signal Integrity
Dec 2007
Digital designs have not traditionally suffered by issues associated with transmission line effects. At lower frequencies the signals remain within data characterization and the system performs as...
Provided by Altera
-
White Papers
Performing Equivalent Timing Analysis Between Altera TimeQuest and Xilinx Trace
Nov 2007
Most hardware designers who are qualifying FPGA performance normally run software benchmark comparisons of FPGAs from different vendors to determine which vendor provides the largest margin for...
Provided by Altera
-
White Papers
Floating-Point Compiler: Increasing Performance With Fewer Resources
Nov 2007
Showing new levels of high-performance, high-density, IEEE754-compliant floating-point applications in FPGAs is the focus of this white paper. A new tool is introduced that will allow 100 percent...
Provided by Altera
-
White Papers
FPGA Power Management and Modeling Techniques
Nov 2007
As designs get larger and add more system functions implemented on FPGAs, and as the advanced silicon process technology moves into smaller geometries, power consumption is increasingly a concern...
Provided by Altera
-
White Papers
Intel® Atom™ Developer Program Celebrates One Year with New Name and More
Oct 2010
With its one-year anniversary, the Intel Atom® Developer™ Program has unveiled a new name: the Intel AppUpSM developer program. In addition, app developers can now download the new gold-release...
Provided by Intel Corporation
-
Whitepapers
FPGA and ASIC Implementation of Vedic Multiplier
Jul 2012
The ever increasing demand in enhancing the ability of processors to handle the complex and challenging processes has resulted in the integration of a number of processor cores into one chip....
Provided by International forum of researchers Students and Academician
-
Whitepapers
An XML-Based Collaborative Framework for ASIC EDesign
Jan 2010
Efficient management of the large number of expertise and services required for design and verification of complex integrated circuits demands a collaborative design environment. Such an...
Provided by IBM
-
White Papers
StimulusCache: Boosting Performance of Chip Multiprocessors With Excess Cache
Jan 2010
Technology advances continuously shrink on-chip devices. Consequently, the number of cores in a single Chip Multiprocessor (CMP) is expected to grow in coming years. Unfortunately, with smaller...
Provided by University of Pittsburgh
-
White Papers
ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors
Nov 2008
This paper proposes and studies a hardware-based adaptive controlled migration strategy for managing distributed L2 caches in chip multiprocessors. Building on an area-efficient shared cache...
Provided by Springer Science+Business Media
-
White Papers
Designing Secure Systems on Reconfigurable Hardware
Jul 2008
The extremely high cost of custom ASIC fabrication makes FPGAs an attractive alternative for deployment of custom hardware. Embedded systems based on reconfigurable hardware integrate many...
Provided by Association for Computing Machinery
-
White Papers
Low Power Gated Bus Synthesis Using Shortest-Path Steiner Graph for System-on-Chip Communications
Jul 2009
Power consumption of system-level on-chip communications is becoming more significant in the overall System-On-Chip (SoC) power as technology scales down. In this paper, the authors propose a low...
Provided by Association for Computing Machinery
-
White Papers
OCP-IP Network-on-Chip Benchmarking Workgroup
Dec 2010
This article presents a summary of the work and infrastructure developed by the OCP-IP Network-on-Chip benchmarking workgroup. Network-on-chip (NoC) is an emerging paradigm for interconnecting...
Provided by Tampere University of Technology
-
White Papers
Achieving Fair or Differentiated Cache Sharing in Power-Constrained Chip Multiprocessors
Sep 2009
Limiting the peak power consumption of Chip Multi Processors (CMPs) has recently received a lot of attention. In order to enable chip-level power capping, the peak power consumption of on-chip L2...
Provided by University of Tennessee
-
White Papers
Temperature-Constrained Power Control for Chip Multiprocessors With Online Model Estimation
Jun 2009
As Chip Multiprocessors (CMPs) become the main trend in processor development, various power and thermal management strategies have recently been proposed to optimize system performance while...
Provided by Association for Computing Machinery
-
White Papers
Adaptive Power Control With Online Model Estimation for Chip Multiprocessors
Oct 2010
As Chip Multiprocessors (CMPs) become the main trend in processor development, various power and thermal management strategies have recently been proposed to optimize system performance while...
Provided by University of Tennessee
-
White Papers
A Low-Power Globally Synchronous Locally Asynchronous FFT Processor
Sep 2007
Low-power design became crucial with the widespread use of the embedded systems, where a small battery has to last for a long period. The embedded processors need to efficient in order to achieve...
Provided by Springer Science+Business Media
-
White Papers
FROCM: A Fair and Low-Overhead Method in SMT Processor
Sep 2007
Simultaneous Multithreading (SMT) and Chip Multiprocessors (CMP) processors have emerged as the mainstream computing platform in major market segments, including PC, server, and embedded domains....
Provided by Springer Science+Business Media
-
White Papers
Energy Efficient Packet Classification Hardware Accelerator
Mar 2008
Packet classification is an important function in a router's line-card. Although many excellent solutions have been proposed in the past, implementing high speed packet classification reaching up...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
A Damq Shared Buffer Scheme for Network-on-Chip
Jul 2007
In this paper the authors present a novel shared buffer scheme for network on chip applications. The proposed scheme is based on a dynamically allocated multi queue self-compacting buffer. Two...
Provided by Washington State University
-
White Papers
Reducing Power in Memory Decoders by Means of Selective Precharge Schemes
May 2007
Two novel memory decoder designs for reducing energy consumption and delay are presented in this paper. These two decoding schemes are compared to the conventional NOR decoder. Fewer word lines...
Provided by Washington State University
-
Whitepapers
A New Reduced Clock Power Flip-Flop for Future SOC Applications
Aug 2012
In this paper a novel technique is proposed based on the comparison between Conventional Conditional Data Mapping Flip-flop and Clock Pair Shared D Flip Flop (CPSFF) here the authors are checking...
Provided by IJCTT-International Journal of Computer Trends and Technology
-
Whitepapers
Implementation of SOBEL Edge Detection on FPGA
Jun 2012
The image processing algorithms has been limited to software implementation which is slower due to the limited processor speed. So, a dedicated processor for edge detection is required which was...
Provided by IJCTT-International Journal of Computer Trends and Technology
-
Whitepapers
FPGA Based Area and Throughput Implementation of JH and BLAKE Hash Function
Apr 2012
Implementation of area and throughput of the main building block (compression function) for two SHA-3 candidates BLAKE and JH hash function. The National Institute of Standards and Technology...
Provided by IJCTT-International Journal of Computer Trends and Technology
-
White Papers
Classifying Application Phases in Asymmetric Chip Multiprocessors
Jan 2010
In present study, in order to improve the performance and reduce the amount of power which is dissipated in heterogeneous multi-core processors, the ability of detecting the program execution...
Provided by Iran University of Science and Technology
-
White Papers
Sinusoidal Frequency Doublers Circuit With Low Voltage + 1. 5 Volt CMOS Inverter
Jan 2010
Sinusoidal frequency doublers are popular in telecommunication for example using instrument processing, or circuit analysis in analog processing. The normally, sinusoidal frequency doublers has be...
Provided by Kasem Bundit University
-
White Papers
Adaptive FPGA NoC-Based Architecture for Multispectral Image Correlation
Mar 2008
An adaptive FPGA architecture based on the NoC (Network-on-Chip) approach is used for the multispectral image correlation. This architecture must contain several distance algorithms depending on...
Provided by Cornell University
-
White Papers
A full-Custom ASIC Design of a 8-bit, 25 MHz, Pipeline ADC Using 0.35 um CMOS technology
Nov 2010
The purpose of this project was to design and implement a pipeline Analog-to-Digital Converter using 0.35um CMOS technology. Initial requirements of a 25-MHz conversion rate and 8-bits of...
Provided by Chalmers University of Technology
-
Case Studies
Animation Gets an Energy-Efficient Upgrade
Mar 2010
Maya Entertainment faces the challenge to fulfill the demands to deliver larger, more complex film formats such as High Definition (HD) and stereoscopy, while utilizing the same space. Solution...
Provided by Intel
-
White Papers
Collision Timing Attack when Breaking 42 AES ASIC Cores
Apr 2011
A collision timing attack which exploits the data-dependent timing characteristics of combinational circuits is demonstrated. The attack is based on the correlation collision attack presented at...
Provided by Ruhr-University Bochum
-
White Papers
Complex Event Detection at Wire Speed With FPGAs
Oct 2009
Complex event detection is an advanced form of data stream processing where the stream(s) are scrutinized to identify given event patterns. The challenge for many Complex Event Processing (CEP)...
Provided by VLDB Endowment
-
White Papers
NetThreads: Programming NetFPGA With Threaded Software
Feb 2010
As FPGA-based systems including soft processors become increasingly common, the authors are motivated to better understand the architectural trade-offs and improve the efficiency of these systems....
Provided by University of Toronto
-
White Papers
Designing Modular Hardware Accelerators in C With ROCCC 2.0
May 2010
While FPGA-based hardware accelerators have repeatedly been demonstrated as a viable option, their programmability remains a major barrier to their wider acceptance by application code developers....
Provided by University of California
-
White Papers
Accelerating Dynamic Time Warping Subsequence Search With GPUs and FPGAs
Dec 2010
Many time series data mining problems require subsequence similarity search as a subroutine. Dozens of similarity/distance measures have been proposed in the last decade and there is increasing...
Provided by University of California
-
White Papers
Compiled Hardware Acceleration of Molecular Dynamics Code
Sep 2008
The objective of Molecular Dynamics (MD) simulations is to determine the shape of a molecule in a given biomolecular environment. These simulations are very demanding computationally, where...
Provided by University of California
-
White Papers
Compiler Generated Systolic Arrays For wavefront Algorithm Acceleration on FPGAs
Sep 2008
Wavefront algorithms, such as the Smith-Waterman algorithm, are commonly used in bioinformatics for exact local and global sequence alignment. These algorithms are highly computationally intensive...
Provided by Sandbridge Technologies
-
White Papers
A Compiler Intermediate Representation for Reconfigurable Fabrics
Sep 2008
Configurable computing relies on the expression of a computation as a circuit. Its main purpose is the hardware based acceleration of programs. Configurable computing has received renewed interest...
Provided by Springer Science+Business Media
-
White Papers
Efficient Hardware Code Generation for FPGAs
May 2008
The wider acceptance of FPGAs as a computing device requires a higher level of programming abstraction. ROCCC is an optimizing C to HDL compiler. The authors describe the code generation approach...
Provided by Association for Computing Machinery
-
White Papers
OpenFPGA CoreLib Core Library Interoperability Effort
Mar 2008
This paper begins by summarizing the goals of the OpenFPGA CoreLib Working Group to facilitate the interoperability of FPGA circuit cores within a variety of FPGA design tools, including...
Provided by Reed Elsevier
-
White Papers
Quick Hotspot: A Software Supported Methodology for Supporting Run-Time Thermal Analysis at MPSoC Designs
Jan 2011
Detailed thermal analysis and exploration has recently received significant attention since it is straightforward-related to numerous reliability issues. Furthermore, thermal profiling is a...
Provided by National Technical University of Athens
-
White Papers
Thermal Optimization for Micro-Architectures Through Selective Block Replication
May 2011
Increased power densities result to higher on-chip temperatures, which in turn creates numerous problems tightly firmed to reliability issues. This problem is expected to become even more severe...
Provided by National Technical University of Athens
-
White Papers
Trading Fault-Masking With Performance Overhead for FPGAs
Jan 2011
Reliability issues become an important design concern with technology scaling. This paper introduces a novel methodology for balancing the desired fault masking and the consequence delay and power...
Provided by National Technical University of Athens
-
White Papers
A Framework for Enabling Fault Tolerance in Reconfigurable Architectures
Dec 2009
Fault tolerance is a pre-request not only for safety critical systems, but almost for the majority of applications. However, the additional hardware elements impose performance degradation. In...
Provided by National Technical University of Athens
-
White Papers
Towards Supporting Fault-Tolerance in FPGAs
Apr 2010
This paper proposes a novel methodology for improving reliability of FPGAs without requiring special purpose hardware. In contrast to related approaches that are applied uniformly over the target...
Provided by National Technical University of Athens
-
White Papers
Fault-Free: A Framework for Supporting Fault Tolerance in FPGAs
Nov 2009
In this paper, the authors propose a novel methodology for supporting application mapping onto FPGAs with fault tolerance even if this feature is not supported by the target platform. For the...
Provided by National Technical University of Athens
-
White Papers
Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support
Aug 2007
This paper introduces a software supported methodology for exploring/evaluating 3D FPGA architectures. Two new CAD tools are developed: the 3DPRO for placement and routing on 3D FPGAs and the...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
A Software-Supported Methodology for Designing High-Performance 3D FPGA Architectures
Dec 2007
A software-supported systematic methodology for exploring and evaluating alternative 3D reconfigurable FPGA architectures is introduced. Two new software tools were developed: a placement and...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Three Dimensional FPGA Architectures: A Shift Paradigm for Energy-Performance Efficient DSP Implementations
Jan 2012
Modern applications exhibit increased complexity which introduces extra constraints during implementation related to delay, power consumption and silicon area. This problem is even more important...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
A Novel Methodology for Exploring Interconnection Architectures Targeting 3-D FPGAs
Dec 2008
In current reconfigurable architectures the interconnection structures increasingly contribute more to the delay and power consumption. The demand for increased clock frequencies and logic density...
Provided by National Technical University of Athens
-
White Papers
System-Level Exploration of 3-D Interconnection Schemes
Nov 2008
3-D chip stacking is the big next step in system integration. Even though the process technology is maturing, many issues related to system implementation are not fully understood yet....
Provided by National Technical University of Athens
-
White Papers
A Software-Supported Methodology for Exploring Interconnection Architectures Targeting 3-D FPGAs
Jan 2009
Interconnect structures significantly contribute to the delay, power consumption, and silicon area of modern reconfigurable architectures. The demand for higher clock frequencies and logic...
Provided by National Technical University of Athens
-
White Papers
A Novel Methodology for Architecture-Level Exploration of 3D SoCs
May 2011
Three-Dimensional (3D) integration is an emerging technology that is expected to lead to tremendous benefits in terms of power, delay and silicon area. Moreover, 3D technology continues...
Provided by National Technical University of Athens
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White Papers
CAD Tools for Designing 3D Integrated Systems
Jun 2011
Expectations of consumer for future consumer electronics devices put significant strain on conventional design and manufacturing processes. Integrating more functionality in a smaller form factor...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
A Software-Supported Methodology for Designing General-Purpose Interconnection Networks for Reconfigurable Architectures
Jan 2012
Modern applications realized onto FPGAs exhibit high connectivity demands. Throughout this paper, the authors study the routing constraints of Virtex devices and they propose a systematic...
Provided by Democritus University of Thrace
-
White Papers
Enhanced Core Processor Blocks of OFDM System
Sep 2011
OFDM is a multi carrier modulation technique in which the carriers are Orthogonal to each others as a result of which it provides high bandwidth efficiency and multiple carriers share the data...
Provided by International Journal of Electronics Communication and Computer Engineering
-
White Papers
Fault Detection and Test Minimization Methods for Combinational Circuits - A Survey
Dec 2011
Rapid increase in population increased the usage of digital components dramatically and their production. For profitable income, the cost of the finished product and time taken for marketing the...
Provided by Alagappa University
-
White Papers
A Decade of Productive FPGA Utilization With Genetic Algorithms
Jan 2012
Genetic algorithms are one of the best ways to deal with the optimization problems. They are precisely suitable for mixed combinatorial problems. As genetic algorithms find the solution by...
Provided by Journal of Theoretical and Applied Information Technology
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White Papers
Design and Implementation of Vending Machine Using Verilog HDL
Jan 2012
The vending machines are used to dispenses small different products (snacks, ice creams, cold drinks etc.), when a coin is inserted. These machines can be implemented in different ways by using...
Provided by International Association of Computer Science & Information Technology (IACSIT)
-
White Papers
Modeling of Reliability for Programmable Nanowires Interconnect
Feb 2012
A Field-Programmable Nanowire Interconnect (FPNI) is from hybrid CMOS/nano circuit family, that generalizes CMOL (CMOS/molcular hybrid) proposed by Likharev, that reparieren technology for a...
Provided by International Association of Computer Science & Information Technology (IACSIT)
-
White Papers
Process Induced Random Variation Models of Nanoscale MOS Performance: Efficient Tool for the Nanoscale Regime Analog/mixed Signal CMOS Statistical/variability Aware Design
Jan 2012
In this paper, the novel models of random variation in Ids which is a key parameter of any MOS transistor, have been proposed in this paper as the probability density functions. Both triode and...
Provided by International Association of Computer Science & Information Technology (IACSIT)
-
White Papers
Area-Efficient FPGA Logic Elements: Architecture and Synthesis
Nov 2010
The authors consider architecture and synthesis techniques for FPGA logic elements (function generators) and show that the LUT-based logic elements in modern commercial FPGAs are over-engineered....
Provided by University of Toronto
-
White Papers
Architecture Description and Packing for Logic Blocks With Hierarchy, Modes and Complex Interconnect
Mar 2011
The development of future FPGA fabrics with more sophisticated and complex logic blocks requires a new CAD flow that permits the expression of that complexity and the ability to synthesize to it....
Provided by Association for Computing Machinery
-
White Papers
Reducing FPGA Router Run-Time Through Algorithm and Architecture
Jun 2011
The authors propose a new FPGA routing approach that, when combined with a low-cost architecture change, results in a 34% reduction in router run-time, at the cost of a 3% area overhead, with no...
Provided by University of Toronto
-
White Papers
Latch-Based Performance Optimization for FPGAs
Jun 2011
The authors explore using pulsed latches for timing optimization - a first in the FPGA community. Pulsed latches are transparent latches driven by a clock with a non-standard (non-50%) duty cycle....
Provided by University of Toronto
-
White Papers
Low-Cost Hardware Profiling of Run-Time and Energy in FPGA Embedded Processors
Jun 2011
Field-Programmable Gate Arrays (FPGAs) are a widely used technology in the design of embedded systems due to their improving speed, density and power, steadily decreasing cost, and their...
Provided by University of Toronto
-
White Papers
Charge-Borrowing Decap: A Novel Circuit for Removal of Local Supply Noise Violations
Apr 2009
The authors propose a novel circuit called Charge-Borrowing Decap (CBD) as a drop-in replacement for passive decaps to reduce supply noise for removal of "Hot-spot" IR-drop problems found late in...
Provided by University of British Columbia
-
White Papers
Simultaneous PVT-Tolerant Voltage-Island Formation and Core Placement for Thousand-Core Platforms
Jul 2009
In this paper, the authors propose a novel approach to voltage island formation and core placement for energy optimization in many-core architectures under parameter variations at pre-fabrication...
Provided by University of British Columbia
-
White Papers
Floating-Point FPGA: Architecture and Modeling
Dec 2009
This paper presents an architecture for a reconfigurable device that is specifically optimized for floating-point applications. Fine-grained units are used for implementing control logic and...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering
Dec 2007
This paper describes Glitchless, a circuit-level technique for reducing power in FPGAs by eliminating unnecessary logic transitions called glitches. This is done by adding programmable delay...
Provided by University of British Columbia
-
White Papers
On the Tradeoff Between Power and Flexibility of FPGA Clock Networks
May 2008
FPGA clock networks consume a significant amount of power since they toggle every clock cycle and must be flexible enough to implement the clocks for a wide range of different applications. The...
Provided by Association for Computing Machinery
-
White Papers
Memory Footprint Reduction for FPGA Routing Algorithms
Jan 2008
In this paper, the authors present a technique to reduce the run-time memory footprint of FPGA routing algorithms. These algorithms require a representation of the physical routing resources and...
Provided by University of British Columbia
-
White Papers
A System-Level Stochastic Circuit Generator for FPGA Architecture Evaluation
Sep 2008
The authors describe a stochastic circuit generator that can be used to automatically create benchmark circuits for use in FPGA architecture studies. The circuits consist of a hierarchy of...
Provided by University of British Columbia
-
White Papers
Static and Dynamic Memory Footprint Reduction for FPGA Routing Algorithms
Jan 2009
During routing, memory is required to store both architectural data and temporary routing data. The architectural data is static, and provides a representation of the physical routing resources...
Provided by Association for Computing Machinery
-
White Papers
An Analytical Model Describing the Relationships Between Logic Architecture and FPGA Density
Jun 2008
This paper describes an analytical model, based principally on Rent's Rule, that relates logic architectural parameters to the area efficiency of an FPGA. In particular, the model relates the...
Provided by University of British Columbia
-
White Papers
Wirelength Modeling for Homogeneous and Heterogeneous FPGA Architectural Development
Feb 2009
This paper describes an analytical model that relates the architectural parameters of an FPGA to the average pre-routing wire-length of an FPGA implementation. Both homogeneous and heterogeneous...
Provided by Association for Computing Machinery
-
White Papers
Modeling Post-Techmapping and Post-Clustering FPGA Circuit Depth
Jun 2009
This paper presents an analytical model that relates FPGA architectural parameters to the expected speed of FPGA implementation. More precisely, the model relates the lookup-table size, cluster...
Provided by University of British Columbia
-
White Papers
An Energy and Power Consumption Analysis of FPGA Routing Architectures
Aug 2009
In this paper, the authors evaluate bi-directional and unidirectional FPGA routing architectures in terms of energy and power consumption using an updated power estimation framework compatible...
Provided by Miami University of Ohio
-
White Papers
An Analytical Model Relating FPGA Architecture to Logic Density and Depth
Sep 2010
This paper presents an analytical model that relates FPGA architectural parameters to the logic size and depth of an FPGA implementation. In particular, the model relates the lookup-table size,...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
A New Method for Designing QCA Circuits
Jan 2012
In this paper, the authors tried to solve some of the problems in logical designing based on Quantum-dot Cellular Automata (QCA) technology especially by using Null Convention Logic (NCL) instead...
Provided by International Association of Computer Science & Information Technology (IACSIT)
-
White Papers
Electronic Warfare Design With PLDs and High-Speed Transceivers
Dec 2007
Electronic warfare has become part of the strategic landscape for all warfighters on the ground, at sea, and in the air. Threats change quickly, so fast characterization of the electromagnetic...
Provided by Altera
-
White Papers
Basic Principles of Signal Integrity
Dec 2007
Digital designs have not traditionally suffered by issues associated with transmission line effects. At lower frequencies the signals remain within data characterization and the system performs as...
Provided by Altera
-
White Papers
Performing Equivalent Timing Analysis Between Altera TimeQuest and Xilinx Trace
Nov 2007
Most hardware designers who are qualifying FPGA performance normally run software benchmark comparisons of FPGAs from different vendors to determine which vendor provides the largest margin for...
Provided by Altera
-
White Papers
Floating-Point Compiler: Increasing Performance With Fewer Resources
Nov 2007
Showing new levels of high-performance, high-density, IEEE754-compliant floating-point applications in FPGAs is the focus of this white paper. A new tool is introduced that will allow 100 percent...
Provided by Altera
-
White Papers
FPGA Power Management and Modeling Techniques
Nov 2007
As designs get larger and add more system functions implemented on FPGAs, and as the advanced silicon process technology moves into smaller geometries, power consumption is increasingly a concern...
Provided by Altera
-
White Papers
Intel® Atom™ Developer Program Celebrates One Year with New Name and More
Oct 2010
With its one-year anniversary, the Intel Atom® Developer™ Program has unveiled a new name: the Intel AppUpSM developer program. In addition, app developers can now download the new gold-release...
Provided by Intel Corporation
-
Whitepapers
FPGA and ASIC Implementation of Vedic Multiplier
Jul 2012
The ever increasing demand in enhancing the ability of processors to handle the complex and challenging processes has resulted in the integration of a number of processor cores into one chip....
Provided by International forum of researchers Students and Academician
-
Whitepapers
An XML-Based Collaborative Framework for ASIC EDesign
Jan 2010
Efficient management of the large number of expertise and services required for design and verification of complex integrated circuits demands a collaborative design environment. Such an...
Provided by IBM
-
White Papers
StimulusCache: Boosting Performance of Chip Multiprocessors With Excess Cache
Jan 2010
Technology advances continuously shrink on-chip devices. Consequently, the number of cores in a single Chip Multiprocessor (CMP) is expected to grow in coming years. Unfortunately, with smaller...
Provided by University of Pittsburgh
-
White Papers
ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors
Nov 2008
This paper proposes and studies a hardware-based adaptive controlled migration strategy for managing distributed L2 caches in chip multiprocessors. Building on an area-efficient shared cache...
Provided by Springer Science+Business Media
-
White Papers
Designing Secure Systems on Reconfigurable Hardware
Jul 2008
The extremely high cost of custom ASIC fabrication makes FPGAs an attractive alternative for deployment of custom hardware. Embedded systems based on reconfigurable hardware integrate many...
Provided by Association for Computing Machinery
-
White Papers
Low Power Gated Bus Synthesis Using Shortest-Path Steiner Graph for System-on-Chip Communications
Jul 2009
Power consumption of system-level on-chip communications is becoming more significant in the overall System-On-Chip (SoC) power as technology scales down. In this paper, the authors propose a low...
Provided by Association for Computing Machinery
-
White Papers
OCP-IP Network-on-Chip Benchmarking Workgroup
Dec 2010
This article presents a summary of the work and infrastructure developed by the OCP-IP Network-on-Chip benchmarking workgroup. Network-on-chip (NoC) is an emerging paradigm for interconnecting...
Provided by Tampere University of Technology
-
White Papers
Achieving Fair or Differentiated Cache Sharing in Power-Constrained Chip Multiprocessors
Sep 2009
Limiting the peak power consumption of Chip Multi Processors (CMPs) has recently received a lot of attention. In order to enable chip-level power capping, the peak power consumption of on-chip L2...
Provided by University of Tennessee
-
White Papers
Temperature-Constrained Power Control for Chip Multiprocessors With Online Model Estimation
Jun 2009
As Chip Multiprocessors (CMPs) become the main trend in processor development, various power and thermal management strategies have recently been proposed to optimize system performance while...
Provided by Association for Computing Machinery
-
White Papers
Adaptive Power Control With Online Model Estimation for Chip Multiprocessors
Oct 2010
As Chip Multiprocessors (CMPs) become the main trend in processor development, various power and thermal management strategies have recently been proposed to optimize system performance while...
Provided by University of Tennessee
-
White Papers
A Low-Power Globally Synchronous Locally Asynchronous FFT Processor
Sep 2007
Low-power design became crucial with the widespread use of the embedded systems, where a small battery has to last for a long period. The embedded processors need to efficient in order to achieve...
Provided by Springer Science+Business Media
-
White Papers
FROCM: A Fair and Low-Overhead Method in SMT Processor
Sep 2007
Simultaneous Multithreading (SMT) and Chip Multiprocessors (CMP) processors have emerged as the mainstream computing platform in major market segments, including PC, server, and embedded domains....
Provided by Springer Science+Business Media
-
White Papers
Energy Efficient Packet Classification Hardware Accelerator
Mar 2008
Packet classification is an important function in a router's line-card. Although many excellent solutions have been proposed in the past, implementing high speed packet classification reaching up...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
A Damq Shared Buffer Scheme for Network-on-Chip
Jul 2007
In this paper the authors present a novel shared buffer scheme for network on chip applications. The proposed scheme is based on a dynamically allocated multi queue self-compacting buffer. Two...
Provided by Washington State University
-
White Papers
Reducing Power in Memory Decoders by Means of Selective Precharge Schemes
May 2007
Two novel memory decoder designs for reducing energy consumption and delay are presented in this paper. These two decoding schemes are compared to the conventional NOR decoder. Fewer word lines...
Provided by Washington State University
-
Whitepapers
A New Reduced Clock Power Flip-Flop for Future SOC Applications
Aug 2012
In this paper a novel technique is proposed based on the comparison between Conventional Conditional Data Mapping Flip-flop and Clock Pair Shared D Flip Flop (CPSFF) here the authors are checking...
Provided by IJCTT-International Journal of Computer Trends and Technology
-
Whitepapers
Implementation of SOBEL Edge Detection on FPGA
Jun 2012
The image processing algorithms has been limited to software implementation which is slower due to the limited processor speed. So, a dedicated processor for edge detection is required which was...
Provided by IJCTT-International Journal of Computer Trends and Technology
-
Whitepapers
FPGA Based Area and Throughput Implementation of JH and BLAKE Hash Function
Apr 2012
Implementation of area and throughput of the main building block (compression function) for two SHA-3 candidates BLAKE and JH hash function. The National Institute of Standards and Technology...
Provided by IJCTT-International Journal of Computer Trends and Technology
-
White Papers
Classifying Application Phases in Asymmetric Chip Multiprocessors
Jan 2010
In present study, in order to improve the performance and reduce the amount of power which is dissipated in heterogeneous multi-core processors, the ability of detecting the program execution...
Provided by Iran University of Science and Technology
-
White Papers
Sinusoidal Frequency Doublers Circuit With Low Voltage + 1. 5 Volt CMOS Inverter
Jan 2010
Sinusoidal frequency doublers are popular in telecommunication for example using instrument processing, or circuit analysis in analog processing. The normally, sinusoidal frequency doublers has be...
Provided by Kasem Bundit University
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White Papers
Adaptive FPGA NoC-Based Architecture for Multispectral Image Correlation
Mar 2008
An adaptive FPGA architecture based on the NoC (Network-on-Chip) approach is used for the multispectral image correlation. This architecture must contain several distance algorithms depending on...
Provided by Cornell University
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White Papers
A full-Custom ASIC Design of a 8-bit, 25 MHz, Pipeline ADC Using 0.35 um CMOS technology
Nov 2010
The purpose of this project was to design and implement a pipeline Analog-to-Digital Converter using 0.35um CMOS technology. Initial requirements of a 25-MHz conversion rate and 8-bits of...
Provided by Chalmers University of Technology
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Case Studies
Animation Gets an Energy-Efficient Upgrade
Mar 2010
Maya Entertainment faces the challenge to fulfill the demands to deliver larger, more complex film formats such as High Definition (HD) and stereoscopy, while utilizing the same space. Solution...
Provided by Intel
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White Papers
Collision Timing Attack when Breaking 42 AES ASIC Cores
Apr 2011
A collision timing attack which exploits the data-dependent timing characteristics of combinational circuits is demonstrated. The attack is based on the correlation collision attack presented at...
Provided by Ruhr-University Bochum
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White Papers
Complex Event Detection at Wire Speed With FPGAs
Oct 2009
Complex event detection is an advanced form of data stream processing where the stream(s) are scrutinized to identify given event patterns. The challenge for many Complex Event Processing (CEP)...
Provided by VLDB Endowment
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White Papers
NetThreads: Programming NetFPGA With Threaded Software
Feb 2010
As FPGA-based systems including soft processors become increasingly common, the authors are motivated to better understand the architectural trade-offs and improve the efficiency of these systems....
Provided by University of Toronto
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White Papers
Designing Modular Hardware Accelerators in C With ROCCC 2.0
May 2010
While FPGA-based hardware accelerators have repeatedly been demonstrated as a viable option, their programmability remains a major barrier to their wider acceptance by application code developers....
Provided by University of California
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White Papers
Accelerating Dynamic Time Warping Subsequence Search With GPUs and FPGAs
Dec 2010
Many time series data mining problems require subsequence similarity search as a subroutine. Dozens of similarity/distance measures have been proposed in the last decade and there is increasing...
Provided by University of California
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White Papers
Compiled Hardware Acceleration of Molecular Dynamics Code
Sep 2008
The objective of Molecular Dynamics (MD) simulations is to determine the shape of a molecule in a given biomolecular environment. These simulations are very demanding computationally, where...
Provided by University of California
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White Papers
Compiler Generated Systolic Arrays For wavefront Algorithm Acceleration on FPGAs
Sep 2008
Wavefront algorithms, such as the Smith-Waterman algorithm, are commonly used in bioinformatics for exact local and global sequence alignment. These algorithms are highly computationally intensive...
Provided by Sandbridge Technologies
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White Papers
A Compiler Intermediate Representation for Reconfigurable Fabrics
Sep 2008
Configurable computing relies on the expression of a computation as a circuit. Its main purpose is the hardware based acceleration of programs. Configurable computing has received renewed interest...
Provided by Springer Science+Business Media
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White Papers
Efficient Hardware Code Generation for FPGAs
May 2008
The wider acceptance of FPGAs as a computing device requires a higher level of programming abstraction. ROCCC is an optimizing C to HDL compiler. The authors describe the code generation approach...
Provided by Association for Computing Machinery
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White Papers
OpenFPGA CoreLib Core Library Interoperability Effort
Mar 2008
This paper begins by summarizing the goals of the OpenFPGA CoreLib Working Group to facilitate the interoperability of FPGA circuit cores within a variety of FPGA design tools, including...
Provided by Reed Elsevier
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White Papers
FPGA Based Adaptive Neuro Fuzzy Inference Controller for Full Vehicle Nonlinear Active Suspension Systems
Oct 2010
The conventional controller like the PID controller requires an exact mathematical model of the controlled system to meet as much control objectives as possible. If it is difficult to establish...
Provided by University of Sussex
